ST STM32F3 Series User Manual

The STM32 Cortex-M4 instruction set PM0214
74/262 PM0214 Rev 10
; to a word value and put it in R0
STR R0, [R1, R2, LSL #2]; stores R0 to an address equal to sum of R1
; and four times R2
3.4.4 LDR and STR, unprivileged
Load and Store with unprivileged access.
Syntax
op{type}T{cond} Rt, [Rn {, #offset}]; immediate offset
Where:
• ‘op’ is either LDR (load register) or STR (store register).
• ‘type’ is one of the following:
B: Unsigned byte, zero extends to 32 bits on loads.
SB: Signed byte, sign extends to 32 bits (LDR only).
H: Unsigned halfword, zero extends to 32 bits on loads.
SH: Signed halfword, sign extends to 32 bits (LDR only).
—: Omit, for word.
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• ‘Rt’ is the register to load or store.
• ‘Rn’ is the register on which the memory address is based.
• ‘offset’ is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the
value in Rn.
Operation
These load and store instructions perform the same function as the memory access
instructions with immediate offset (see LDR and STR, immediate offset on page 71). The
difference is that these instructions have only unprivileged access even when used in
privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as
normal memory access instructions with immediate offset.
Restrictions
In these instructions:
• Rn must not be PC.
• Rt must be neither SP nor PC.
Condition flags
These instructions do not change the flags.
Examples
STRBTEQ R4, [R7] ; conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT R2, [R2, #8]; load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access

ST STM32F3 Series Specifications

General

Series	STM32F3
Core	ARM Cortex-M4
Max CPU Frequency	72 MHz
Operating Voltage	2.0 V to 3.6 V
GPIO Pins	Up to 80
Timers	Advanced-control, general-purpose, basic timers
ADC	12-bit
DAC	12-bit
Communication Interfaces	USART, SPI, I2C, CAN, USB
Operating Temperature	-40°C to 85°C
Package	LQFP, UFQFPN, WLCSP

Summary

Introduction

1 About this document

1.1 Typographical conventions

Conventions used in the document for formatting text and code elements.

1.2 List of abbreviations for registers

Abbreviations used in register descriptions.

1.3 About the STM32 Cortex-M4 processor and core peripherals

Overview of the processor's features and integrated peripherals.

2 The Cortex-M4 processor

2.1 Programmers model

Describes the programmer's model, processor modes, privilege levels, and stacks.

2.2 Memory model

Details the processor memory map, access behavior, and bit-banding features.

2.3 Exception model

Explains the exception model, states, types, handlers, and priorities.

2.4 Fault handling

Details fault types, escalation, status registers, and lockup.

2.5 Power management

Describes mechanisms for entering and waking up from sleep modes.

3 The STM32 Cortex-M4 instruction set

3.1 Instruction set summary

Overview of the instruction set and supported instructions.

3.2 CMSIS intrinsic functions

CMSIS intrinsic functions for generating Cortex-M4 instructions.

3.3 About the instruction descriptions

Explains how instruction descriptions are presented in the document.

3.4 Memory access instructions

Details instructions for accessing memory.

3.5 General data processing instructions

Covers general-purpose data processing instructions.

3.6 Multiply and divide instructions

Describes instructions for multiplication and division operations.

3.7 Saturating instructions

Explains instructions that perform saturating arithmetic.

3.8 Packing and unpacking instructions

Instructions for packing and unpacking data.

3.9 Bitfield instructions

Instructions for operating on bitfields within registers.

3.10 Floating-point instructions

Instructions for floating-point operations using the FPU.

3.11 Miscellaneous instructions

Other Cortex-M4 instructions not categorized elsewhere.

4 Core peripherals

4.1 About the STM32 Cortex-M4 core peripherals

Overview of core peripherals and their memory map in the PPB.

4.2 Memory protection unit (MPU)

Details the MPU's functionality for memory protection and region management.

4.3 Nested vectored interrupt controller (NVIC)

Describes the NVIC's support for interrupts, priorities, and tail-chaining.

4.4 System control block (SCB)

Provides system implementation info and control for exceptions.

4.5 SysTick timer (STK)

Details the SysTick timer, its registers, and usage hints.

4.6 Floating point unit (FPU)

Explains the FPU's functionality, registers, and enabling.

5 Revision history