The STM32 Cortex-M4 instruction set PM0214
74/262 PM0214 Rev 10
; to a word value and put it in R0
STR R0, [R1, R2, LSL #2]; stores R0 to an address equal to sum of R1
; and four times R2
3.4.4 LDR and STR, unprivileged
Load and Store with unprivileged access.
Syntax
op{type}T{cond} Rt, [Rn {, #offset}]; immediate offset
Where:
• ‘op’ is either LDR (load register) or STR (store register).
• ‘type’ is one of the following:
B: Unsigned byte, zero extends to 32 bits on loads.
SB: Signed byte, sign extends to 32 bits (LDR only).
H: Unsigned halfword, zero extends to 32 bits on loads.
SH: Signed halfword, sign extends to 32 bits (LDR only).
—: Omit, for word.
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• ‘Rt’ is the register to load or store.
• ‘Rn’ is the register on which the memory address is based.
• ‘offset’ is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the
value in Rn.
Operation
These load and store instructions perform the same function as the memory access
instructions with immediate offset (see LDR and STR, immediate offset on page 71). The
difference is that these instructions have only unprivileged access even when used in
privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as
normal memory access instructions with immediate offset.
Restrictions
In these instructions:
• Rn must not be PC.
• Rt must be neither SP nor PC.
Condition flags
These instructions do not change the flags.
Examples
STRBTEQ R4, [R7] ; conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT R2, [R2, #8]; load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
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