PM0214 Rev 9 99/262
PM0214 The STM32 Cortex-M4 instruction set
261
; Adds top halfword of R3 with bottom halfword of R2 and
; writes to top halfword of R7.
3.5.15 TST and TEQ
Test bits and Test Equivalence.
Syntax
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
Where:
• ‘cond’ is an optional condition code (see Conditional execution on page 65).
• ‘Rn’ is the register holding the first operand.
• ‘Operand2’ is a flexible second operand (see Flexible second operand on page 60) for
details of the options.
Operation
These instructions test the value in a register against operand2. They update the condition
flags based on the result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of
operand2. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an operand2 constant that
has that bit set to 1 and all other bits cleared to 0.
The TEQ instruction performs a bitwise exclusive OR operation on the value in Rn and the
value of operand2. This is the same as the EORS instruction, except that it discards the
result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the
logical exclusive OR of the sign bits of the two operands.
Restrictions
Do not use either SP or PC.
Condition flags
These instructions:
• Update the N and Z flags according to the result
• Can update the C flag during the calculation of operand2 (see Flexible second operand
on page 60).
• Do not affect the V flag
Examples
TST R0, #0x3F8 ; perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
TEQEQ R10, R9 ; conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded
To Next Page
Loading...
Need help?
General
