PM0214 Rev 9 165/262
PM0214 The STM32 Cortex-M4 instruction set
261
3.10.15 VMOV scalar to Arm core register
Transfers one word of a doubleword floating-point register to an Arm core register.
Syntax
VMOV{cond} Rt, Dn[x]
Where:
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• ‘Rt’ is the destination Arm core register.
• ‘Dn’ is the 64-bit doubleword register.
• ‘x’ Specifies which half of the doubleword register to use:
If x is 0, use lower half, if x is 1, use upper half.
Operation
This instruction transfers one word from the upper or lower half of a doubleword floating-
point register to an Arm core register.
Restrictions
Rt cannot be PC or SP.
Condition flags
These instructions do not change the flags.
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