PM0214 Rev 9 161/262
PM0214 The STM32 Cortex-M4 instruction set
261
3.10.11 VLDR
Loads a single extension register from memory
Syntax
VLDR{cond}{.64} Dd, [Rn{#imm}]
VLDR{cond}{.64} Dd, label
VLDR{cond}{.64} Dd, [PC, #imm}]
VLDR{cond}{.32} Sd, [Rn {, #imm}]
VLDR{cond}{.32} Sd, label
VLDR{cond}{.32} Sd, [PC, #imm]
Where:
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• ‘64, 32 are the optional data size specifiers.
• Dd is the destination register for a doubleword load.
• Sd is the destination register for a singleword load.
• Rn is the base register. The SP can be used.
• imm is the + or - immediate offset used to form the address.
Permitted address values are multiples of 4 in the range 0 to 1020.
• label is the label of the literal data item to be loaded.
Operation
This instruction loads a single extension register from memory, using a base address from
an Arm core register, with an optional offset.
Restrictions
There are no restrictions.
Condition flags
These instructions do not change the flags.
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