Core peripherals PM0214
214/262 PM0214 Rev 9
4.3.6 Interrupt active bit register x (NVIC_IABRx)
Address offset: 0x300 + 0x04 * x, (x = 0 to 7)
Reset value: 0x0000 0000
Required privilege: Privileged
NVIC_IABR0 bits 0 to 31 are for interrupt 0 to 31, respectively
NVIC_IABR1 bits 0 to 31 are for interrupt 32 to 63, respectively
....
NVIC_IABR6 bits 0 to 31 are for interrupt 192 to 223, respectively
NVIC_IABR7 bits 0 to 15 are for interrupt 224 to 239, respectively
Note: The number of interrupts is product-dependent. Refer to reference manual/datasheet of
relevant STM32 product for related information.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE[31:16]
rrrrrr r r r r rrrrrr
1514131211109876543210
ACTIVE[15:0]
rrrrrr r r r r rrrrrr
Bits 31:0 ACTIVE: Interrupt active flags
0: Interrupt not active
1: Interrupt active
A bit reads as 1 if the status of the corresponding interrupt is active or active and pending.
Bits 16 to 31 of the NVIC_IABR7 register are reserved.
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