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ST STM32F4 Series User Manual

ST STM32F4 Series
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Core peripherals PM0214
256/262 PM0214 Rev 9
Bit 28 V: Overflow condition code flag. Floating-point comparison operations update this flag. For more
details on the result, refer to Table 57.
0: Operation did not result in an overflow
1: Operation resulted in an overflow.
Bit 27 Reserved.
Bit 26 AHP: Alternative half-precision control bit:
0: IEEE half-precision format selected.
1: Alternative half-precision format selected.
Bit 25 DN: Default NaN mode control bit:
0: NaN operands propagate through to the output of a floating-point operation.
1: Any operation involving one or more NaNs returns the Default NaN.
Bit 24 FZ: Flush-to-zero mode control bit:
0: Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the
IEEE 754 standard.
1: Flush-to-zero mode enabled.
Bits 23:22 RMode: Rounding Mode control field. The specified rounding mode is used by almost all
floating-point instructions:
0b00: Round to nearest (RN) mode
0b01: Round towards plus infinity (RP) mode
0b10: Round towards minus infinity (RM) mode
0b11: Round towards zero (RZ) mode.
Bit 21:8 Reserved.
Bit 7 IDC: Input denormal cumulative exception bit. Cumulative exception bit for floating-point
exception.
1: Indicates that the corresponding exception occurred since 0 was last written to it.
Bit 6:5 Reserved
Bit 4 IXC: Inexact cumulative exception bit. Cumulative exception bit for floating-point exception.
1: Indicates that the corresponding exception occurred since 0 was last written to it.
Bit 3 UFC: Underflow cumulative exception bit. Cumulative exception bit for floating-point exception.
1: Indicates that the corresponding exception occurred since 0 was last written to it.
Bit 2 OFC: Overflow cumulative exception bit. Cumulative exception bit for floating-point exception.
1: Indicates that the corresponding exception occurred since 0 was last written to it.
Bit 1 DZC: Division by zero cumulative exception bit. Cumulative exception bit for floating-point
exception. 1: Indicates that the corresponding exception occurred since 0 was last written to it.
Bit 0 IOC: Invalid operation cumulative exception bit. Cumulative exception bit for floating-point
exception. 1: Indicates that the corresponding exception occurred since 0 was last written to it.
Table 57. Effect of a Floating-point comparison on the condition flags
Comparison result N Z C V
Equal 0 1 1 0
Less than 1 0 0 0
Greater than 0 0 1 0
Unordered 0 0 1 1

Table of Contents

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ST STM32F4 Series Specifications

General IconGeneral
SeriesSTM32F4
CoreARM Cortex-M4
Clock SpeedUp to 180 MHz
Flash MemoryUp to 2 MB
RAMUp to 384 KB
Operating Voltage1.8 V to 3.6 V
DAC12-bit, up to 2 channels
TimersUp to 17 timers
Communication InterfacesUSB, CAN, SPI, I2C, USART, Ethernet
Operating Temperature-40°C to 85°C
PackageLQFP, WLCSP, BGA

Summary

Introduction to the STM32 Cortex-M4 Programming Manual

Cortex-M4 Processor Features and Benefits

Summarizes key advantages: outstanding performance, enhanced debug, efficient core, low power, and security.

Reference Documents for STM32 Cortex-M4

Lists datasheets and reference manuals available from STMicroelectronics website for further details.

About this document

Typographical Conventions Used

Explains conventions for highlighting important notes, cross-references, and code elements.

Abbreviations for Registers

Lists common abbreviations used in register descriptions, such as (rw), (r), and (w).

STM32 Cortex-M4 Processor and Core Peripherals Overview

Introduces the Cortex-M4 processor, its architecture, and integrated core peripherals.

The Cortex-M4 Processor

Cortex-M4 Programmers Model

Describes processor modes, privilege levels, execution states, and stack usage.

Cortex-M4 Memory Model

Explains the memory map, access behavior, and bit-banding features.

Cortex-M4 Exception Model

Covers exception states, types, handlers, priorities, and grouping mechanisms.

The STM32 Cortex-M4 Instruction Set

Instruction Set Summary and Syntax

Lists supported instructions, syntax conventions, and flexible operand usage.

Memory Access Instructions

Details instructions for loading and storing data from memory.

General Data Processing Instructions

Covers arithmetic, logical, shift, and data manipulation instructions.

Multiply and Divide Instructions

Explains signed/unsigned multiply, accumulate, divide, and saturation instructions.

Saturating Instructions

Describes instructions performing saturation arithmetic on signed/unsigned values.

Core Peripherals

Nested Vectored Interrupt Controller (NVIC)

Details the NVIC's interrupt handling, priority levels, and registers.

System Control Block (SCB) Registers

Explains SCB registers for system control, configuration, and exception reporting.

SysTick Timer (STK) Functionality

Describes the SysTick timer for system timing and RTOS tick generation.

Document Revision History

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