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PM0214 Rev 9 185/262

PM0214 The STM32 Cortex-M4 instruction set

261

3.11.5 ISB

Instruction synchronization barrier.

Syntax

ISB{cond}

Where: ‘cond’ is an optional condition code, see Conditional execution on page 65.

Operation

ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so

that all instructions following the ISB are fetched from cache or memory again, after the ISB

instruction is completed.

Condition flags

This instruction does not change the flags.

Examples

ISB ; Instruction Synchronisation Barrier

Table 1. Applicable Products1
Table of Contents2
About this Document12
Typographical Conventions12
List of Abbreviations for Registers12
About the STM32 Cortex-M4 Processor and Core Peripherals13
Figure 1. STM32 Cortex-M4 Implementation13
System Level Interface14
Integrated Configurable Debug14
Cortex-M4 Processor Features and Benefits Summary15
Cortex-M4 Core Peripherals16
The Cortex-M4 Processor17
Programmers Model17
Processor Mode and Privilege Levels for Software Execution17
Stacks17
Core Registers18
Table 2. Summary of Processor Mode, Execution Privilege Level, and Stack Usage18
Table 3. Core Register Set Summary18
Figure 2. Processor Core Registers18
Table 4. PSR Register Combinations20
Figure 3. APSR, IPSR and EPSR Bit Assignment20
Figure 4. PSR Bit Assignment20
Table 5. APSR Bit Definitions21
Table 6. IPSR Bit Definitions22
Table 7. EPSR Bit Definitions23
Table 8. PRIMASK Register Bit Definitions24
Table 9. FAULTMASK Register Bit Definitions24
Figure 5. PRIMASK Bit Assignment24
Figure 6. FAULTMASK Bit Assignment24
Table 10. BASEPRI Register Bit Assignment25
Table 11. CONTROL Register Bit Definitions25
Figure 7. BASEPRI Bit Assignment25
Exceptions and Interrupts26
Data Types26
The Cortex Microcontroller Software Interface Standard (CMSIS)26
Memory Model28
Figure 8. Memory Map28
Memory Regions, Types and Attributes29
Memory System Ordering of Memory Accesses29
Table 12. Ordering of Memory Accesses29
Behavior of Memory Accesses30
Table 13. Memory Access Behavior30
Software Ordering of Memory Accesses31
Bit-Banding32
Table 14. SRAM Memory Bit-Banding Regions32
Table 15. Peripheral Memory Bit-Banding Regions32
Figure 9. Bit-Band Mapping33
Memory Endianness34
Synchronization Primitives34
Figure 10. Little-Endian Example34
Programming Hints for the Synchronization Primitives36
Table 16. CMSIS Functions for Exclusive Access Instructions36
Exception Model37
Exception States37
Exception Types37
Table 17. Properties of the Different Exception Types38
Exception Handlers39
Vector Table40
Figure 11. Vector Table40
Exception Priorities41
Interrupt Priority Grouping41
Exception Entry and Return42
Figure 12. Cortex-M4 Stack Frame Layout43
Fault Handling44
Table 18. Exception Return Behavior44
Fault Types45
Table 19. Faults45
Fault Escalation and Hard Faults46
Fault Status Registers and Fault Address Registers47
Lockup47
Power Management47
Table 20. Fault Status and Fault Address Registers47
Entering Sleep Mode48
Wakeup from Sleep Mode48
External Event Input / Extended Interrupt and Event Input49
Power Management Programming Hints49
The STM32 Cortex-M4 Instruction Set50
Instruction Set Summary50
Table 21. Cortex-M4 Instructions50
CMSIS Intrinsic Functions58
Table 22. CMSIS Intrinsic Functions to Generate some Cortex-M4 Instructions59
Table 23. CMSIS Intrinsic Functions to Access the Special Registers59
About the Instruction Descriptions60
Operands60
Restrictions When Using PC or SP60
Flexible Second Operand60
Shift Operations62
Figure 13. ASR #362
Figure 14. LSR #363
Figure 15. LSL #363
Figure 16. ROR #364
Figure 17. RRX #364
Address Alignment65
PC-Relative Expressions65
Conditional Execution65
Table 24. Condition Code Suffixes67
Instruction Width Selection68
Memory Access Instructions69
Table 25. Memory Access Instructions69
Adr70
LDR and STR, Immediate Offset71
Table 26. Immediate, Pre-Indexed and Post-Indexed Offset Ranges72
LDR and STR, Register Offset73
LDR and STR, Unprivileged74
LDR, PC-Relative75
Table 27. Label-PC Offset Ranges75
LDM and STM76
PUSH and POP78
LDREX and STREX79
Clrex80
General Data Processing Instructions81
Table 28. Data Processing Instructions81
ADD, ADC, SUB, SBC, and RSB83
AND, ORR, EOR, BIC, and ORN85
ASR, LSL, LSR, ROR, and RRX86
Clz87
CMP and CMN88
MOV and MVN89
Movt91
REV, REV16, REVSH, and RBIT92
SADD16 and SADD893
SHADD16 and SHADD894
SHASX and SHSAX95
SHSUB16 and SHSUB896
SSUB16 and SSUB897
SASX and SSAX98
TST and TEQ99
UADD16 and UADD8100
UASX and USAX101
UHADD16 and UHADD8102
UHASX and UHSAX103
UHSUB16 and UHSUB8104
Sel105
Usad8106
Usada8107
USUB16 and USUB8108
Multiply and Divide Instructions109
Table 29. Multiply and Divide Instructions109
MUL, MLA, and MLS110
UMULL, UMAAL and UMLAL111
SMLA and SMLAW112
Smlad114
SMLAL and SMLALD115
SMLSD and SMLSLD117
SMMLA and SMMLS119
Smmul120
SMUAD and SMUSD121
SMUL and SMULW122
UMULL, UMLAL, SMULL, and SMLAL123
SDIV and UDIV124
Saturating Instructions125
Table 30. Saturating Instructions125
SSAT and USAT126
SSAT16 and USAT16127
QADD and QSUB128
QASX and QSAX129
QDADD and QDSUB130
UQASX and UQSAX131
UQADD and UQSUB132
Packing and Unpacking Instructions134
Table 31. Packing and Unpacking Instructions134
PKHBT and PKHTB135
SXT and UXT136
SXTA and UXTA137
Bitfield Instructions138
Table 32. Instructions that Operate on Adjacent Sets of Bits138
BFC and BFI139
SBFX and UBFX140
SXT and UXT141
Branch and Control Instructions142
B, BL, BX, and BLX142
Table 33. Branch and Control Instructions142
Table 34. Branch Ranges143
CBZ and CBNZ144
TBB and TBH147
Floating-Point Instructions149
Table 35. Floating-Point Instructions149
Vabs151
Vadd152
Vcmp, Vcmpe153
VCVT, VCVTR between Floating-Point and Integer154
VCVT between Floating-Point and Fixed-Point155
Vcvtb, Vcvtt156
VDIV157
Vfma, Vfms158
Vfnma, Vfnms159
Vldm160
Vldr161
Vlma, Vlms162
VMOV Immediate163
VMOV Register164
VMOV Scalar to Arm Core Register165
VMOV Arm Core Register to Single Precision166
VMOV Two Arm Core Registers to Two Single Precision167
VMOV Arm Core Register to Scalar168
Vmrs169
Vmsr170
Vmul171
Vneg172
Vnmla, Vnmls, Vnmul173
Vpop174
Vpush175
Vsqrt176
Vstm177
Vstr178
Vsub179
Miscellaneous Instructions180
Table 36. Miscellaneous Instructions180
Bkpt181
Cps182
Dmb183
Dsb184
Isb185
Mrs186
Msr187
Nop188
Sev189
Svc190
Wfe191
Wfi192
Core Peripherals193
About the STM32 Cortex-M4 Core Peripherals193
Memory Protection Unit (MPU)193
Table 37. STM32 Core Peripheral Register Regions193
Table 38. Memory Attributes Summary194
MPU Access Permission Attributes195
Table 39. TEX, C, B, and S Encoding195
Table 40. Cache Policy for Memory Attribute Encoding195
MPU Mismatch196
Updating an MPU Region196
Table 41. AP Encoding196
Figure 18. Subregion Example198
MPU Design Hints and Tips199
Table 42. Memory Region Attributes for STM32199
MPU Type Register (MPU_TYPER)200
MPU Control Register (MPU_CTRL)201
MPU Region Number Register (MPU_RNR)202
MPU Region Base Address Register (MPU_RBAR)203
MPU Region Attribute and Size Register (MPU_RASR)204
Table 43. Example SIZE Field Values205
MPU Register Map206
Table 44. MPU Register Map and Reset Values206
Nested Vectored Interrupt Controller (NVIC)208
Table 45. NVIC Register Summary208
Accessing the Cortex-M4 NVIC Registers Using CMSIS209
Table 46. CMSIS Access NVIC Functions209
Interrupt Set-Enable Register X (Nvic_Iserx)210
Interrupt Clear-Enable Register X (Nvic_Icerx)211
Interrupt Set-Pending Register X (Nvic_Isprx)212
Interrupt Clear-Pending Register X (Nvic_Icprx)213
Interrupt Active Bit Register X (Nvic_Iabrx)214
Interrupt Priority Register X (Nvic_Iprx)215
Table 47. Nvic_Iprx Bit Assignment215
Figure 19. Mapping of IP[N] Fields in Nvic_Iprx Registers215
Software Trigger Interrupt Register (NVIC_STIR)216
Level-Sensitive and Pulse Interrupts217
NVIC Design Hints and Tips218
Table 48. CMSIS Functions for NVIC Control218
NVIC Register Map219
Table 49. NVIC Register Map and Reset Values219
System Control Block (SCB)221
Table 50. Summary of the System Control Block Registers221
Auxiliary Control Register (ACTLR)222
CPUID Base Register (CPUID)224
Interrupt Control and State Register (ICSR)225
Vector Table Offset Register (VTOR)227
Application Interrupt and Reset Control Register (AIRCR)228
Table 51. Priority Grouping229
System Control Register (SCR)230
Configuration and Control Register (CCR)231
System Handler Priority Registers (Shprx)233
Table 52. System Fault Handler Priority Fields233
System Handler Control and State Register (SHCSR)235
Configurable Fault Status Register (CFSR; UFSR+BFSR+MMFSR)237
Figure 20. CFSR Subregisters237
Usage Fault Status Register (UFSR)238
Bus Fault Status Register (BFSR)239
Memory Management Fault Address Register (MMFSR)240
Hard Fault Status Register (HFSR)241
Memory Management Fault Address Register (MMFAR)242
Bus Fault Address Register (BFAR)242
Auxiliary Fault Status Register (AFSR)243
System Control Block Design Hints and Tips243
SCB Register Map244
Table 53. SCB Register Map and Reset Values244
Systick Timer (STK)246
Table 54. System Timer Registers Summary246
Systick Control and Status Register (STK_CTRL)247
Systick Reload Value Register (STK_LOAD)248
Systick Current Value Register (STK_VAL)249
Systick Calibration Value Register (STK_CALIB)250
Systick Design Hints and Tips250
Systick Register Map251
Table 55. Systick Register Map and Reset Values251
Floating Point Unit (FPU)252
Table 56. Cortex-M4F Floating-Point System Registers252
Coprocessor Access Control Register (CPACR)253
Floating-Point Context Control Register (FPCCR)253
Floating-Point Context Address Register (FPCAR)255
Floating-Point Status Control Register (FPSCR)255
Table 57. Effect of a Floating-Point Comparison on the Condition Flags256
Floating-Point Default Status Control Register (FPDSCR)257
Enabling the FPU257
Enabling and Clearing FPU Exception Interrupts258
Revision History260
Table 58. Document Revision History260

Brand	ST
Model	STM32F4 Series
Category	Computer Hardware
Language	English

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