PM0214 Rev 9 95/262
PM0214 The STM32 Cortex-M4 instruction set
261
3.5.11 SHASX and SHSAX
Signed Halving Add and Subtract with Exchange / Signed Halving Subtract and Add with
Exchange.
Syntax
op{cond} {Rd}, Rn, Rm
Where:
• op is any of the following:
SHASX: Add and subtract with exchange and halving.
SHSAX: Subtract and add with exchange and halving.
• ‘cond’ is an optional condition code (see Conditional execution on page 65):
• ‘Rd’ is the destination register:
• ‘Rn’ is the register holding the operand:
• ‘Rn’, ‘Rm’ are the registers holding the first and second operands:
Operation
The SHASX instruction:
1. Adds the top halfword of the first operand to the bottom halfword of second operand.
2. Writes the halfword result of the addition to the top halfword of the destination register,
shifted by one bit to the right, causing a divide by two, or halving.
3. Subtracts the top halfword of the second operand from the bottom highword of the first
operand.
4. Writes the halfword result of the division in the bottom halfword of the destination
register, shifted by one bit to the right, causing a divide by two, or halving.
The SHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first
operand.
2. Writes the halfword result of the addition to the bottom halfword of the destination
register, shifted by one bit to the right, causing a divide by two, or halving.
3. Adds the bottom halfword of the first operand to the top halfword of the second
operand.
4. Writes the halfword result of the division in the top halfword of the destination register,
shifted by one bit to the right, causing a divide by two, or halving.
Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not affect the condition code flags.
Examples
SHASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2
; and writes halved result to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
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