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ST STM32H725 User Manual
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Figure 4.
VDD33USB connected to V
DD
power supply
time
Power-on
Power-
down
Operating mode
V
DD33USB_MAX
=
V
DD_MAX
V
DD_MIN
V
DD
V
DD=
V
DD33USB
USB
functional
V
DDUSB_MIN
Figure 5.
VDD33USB connected to external power supply
VDD33USB
forbidden
area
time
V
DD33USB_MAX
USB
functional
V
DD33USB
forbidden
area
V
DD33USB
Power-on
Power-
down
Operating mode
V
DD
V
DD33USB_MIN
V
DD_MIN
USB
functional
AN5419
Introduction
AN5419
-
Rev 2
page 1
1/50
10
12
Table of Contents
General Information
2
Power Supplies
3
Introduction
3
Table 1. PWR Input/Output Signals Connected to Package Pins/Balls
5
Figure 2. System Supply Configuration
5
External Power Supplies and Components
7
Digital Circuit Core Supply (Vcore)
10
Independent Analog Supply and Reference Voltage
10
Independent USB Transceiver Power Supply
10
Table 2. Power Supply Connection
10
Figure 1. Power Supplies
10
Figure 4. VDD33USB Connected to
11
Figure 5. VDD33USB Connected to External Power Supply
11
Battery Backup Domain
12
LDO Voltage Regulator
12
Figure 6. VDD50USB Power Supply
12
SMPS Step-Down Converter
14
Reset and Power Supply Supervisor
15
Power-On Reset (Por)/Power-Down Reset (PDR)
15
Figure 7. Power on Reset/Power down Reset Waveform
15
Brownout Reset (BOR)
16
Programmable Voltage Detector (PVD)
16
Analog Voltage Detector (AVD)
17
System Reset
17
Bypass Mode
17
Figure 9. Reset Circuit
17
Clocks
18
Introduction
18
Figure 10. Clock Generation and Clock Tree
18
HSE and LSE Bypass (External User Clock)
22
External Crystal/Ceramic Resonator (HSE Crystal)
22
LSE Oscillator Clock
23
Clock Security System (CSS)
23
Clock Recovery System (CRS)
23
Alternate Function Mapping to Pins
24
Analog Inputs for ADC1, ADC2 and ADC3
24
Packages Having Pxy_C and Pxy Pads Available
24
Figure 12. Analog Inputs for ADC1 and ADC2
24
Packages Having Pxy_C but Not the Peer Pxy
25
Package Having Pxy Available but nor the Peer Pxy_C
25
Boot Configuration
26
Boot Mode Selection
26
Table 5. Boot Modes
26
Boot Pin Connection
27
System Bootloader Mode
27
Table 6. STM32H723/733, STM32H725/735 and STM32H730 Microcontroller Bootloader Communication Peripherals
27
Figure 13. Boot Mode Selection Implementation Example
27
Debug Management
28
Introduction
28
SWJ Debug Port (Serial Wire and JTAG)
28
TPIU Trace Port
28
External Debug Trigger
28
Figure 14. Host to Board Connection
28
Pinout and Debug Port Pins
29
SWJ Debug Port Pins
29
Flexible SWJ-DP Pin Assignment
29
Table 9. SWJ Debug Port Pins
29
Table 10. Flexible SWJ-DP Assignment
29
Internal Pull-Up and Pull-Down on JTAG Pins
30
SWJ Debug Port Connection with Standard JTAG Connector
30
Figure 15. JTAG Connector Implementation
30
Recommendations
31
Printed Circuit Board
31
Component Position
31
Ground and Power Supply (VSS,VDD)
31
Decoupling
31
Figure 16. Typical Layout for V
31
DD /VSS Pair
31
Other Signals
32
Unused I/Os and Features
32
Reference Design
33
Description
33
Recommended PCB Routing Guidelines for STM32H723/733, STM32H725/735 and STM32H730 Microcontrollers
34
PCB Stack-Up
34
Crystal Oscillator
35
Power Supply Decoupling
35
Figure 19. Decoupling Capacitor Placement Depending on Package Type
35
Figure 20. Example of Decoupling Capacitor Placed Underneath
35
High Speed Signal Layout
36
SDMMC Bus Interface
36
Figure 21. Microsd Card Interconnection Example
36
Flexible Memory Controller (FMC) Interface
37
Figure 22. SD Card Interconnection Example
37
Octo-SPI Interface
38
Figure 23. Octo-SPI Interconnection Example
38
DFSDM Interface
40
Figure 25. Stereo Microphone Interconnection
40
Embedded Trace Macrocell (ETM)
41
Use Case Examples
42
Table 11. Use Case Examples
42
Conclusion
43
Revision History
44
Table 4. Clock Source Generation
44
Figure 3. Power Supply Component Layout
44
Table of Contents
45
Contents
45
List of Tables
48
List of Figures
49
4
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ST STM32H725 Specifications
General
Brand
ST
Model
STM32H725
Category
Microcontrollers
Language
English
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