ST STM32H725

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9.4.4 DFSDM interface .......................................................40

9.4.5 Embedded trace macrocell (ETM)...........................................41

10 Use case examples ...............................................................42

11 Conclusion .......................................................................43

Revision history .......................................................................44

Contents ..............................................................................45

List of tables ..........................................................................48

List of figures..........................................................................49

AN5419

Contents

AN5419 - Rev 2

page 47/50

Main Page

General Information2
Power Supplies3
Introduction3
Table 1. PWR Input/Output Signals Connected to Package Pins/Balls5
Figure 2. System Supply Configuration5
External Power Supplies and Components7
Digital Circuit Core Supply (Vcore)10
Independent Analog Supply and Reference Voltage10
Independent USB Transceiver Power Supply10
Table 2. Power Supply Connection10
Figure 1. Power Supplies10
Figure 4. VDD33USB Connected to11
Figure 5. VDD33USB Connected to External Power Supply11
Battery Backup Domain12
LDO Voltage Regulator12
Figure 6. VDD50USB Power Supply12
SMPS Step-Down Converter14
Reset and Power Supply Supervisor15
Power-On Reset (Por)/Power-Down Reset (PDR)15
Figure 7. Power on Reset/Power down Reset Waveform15
Brownout Reset (BOR)16
Programmable Voltage Detector (PVD)16
Analog Voltage Detector (AVD)17
System Reset17
Bypass Mode17
Figure 9. Reset Circuit17
Clocks18
Introduction18
Figure 10. Clock Generation and Clock Tree18
HSE and LSE Bypass (External User Clock)22
External Crystal/Ceramic Resonator (HSE Crystal)22
LSE Oscillator Clock23
Clock Security System (CSS)23
Clock Recovery System (CRS)23
Alternate Function Mapping to Pins24
Analog Inputs for ADC1, ADC2 and ADC324
Packages Having Pxy_C and Pxy Pads Available24
Figure 12. Analog Inputs for ADC1 and ADC224
Packages Having Pxy_C but Not the Peer Pxy25
Package Having Pxy Available but nor the Peer Pxy_C25
Boot Configuration26
Boot Mode Selection26
Table 5. Boot Modes26
Boot Pin Connection27
System Bootloader Mode27
Table 6. STM32H723/733, STM32H725/735 and STM32H730 Microcontroller Bootloader Communication Peripherals27
Figure 13. Boot Mode Selection Implementation Example27
Debug Management28
Introduction28
SWJ Debug Port (Serial Wire and JTAG)28
TPIU Trace Port28
External Debug Trigger28
Figure 14. Host to Board Connection28
Pinout and Debug Port Pins29
SWJ Debug Port Pins29
Flexible SWJ-DP Pin Assignment29
Table 9. SWJ Debug Port Pins29
Table 10. Flexible SWJ-DP Assignment29
Internal Pull-Up and Pull-Down on JTAG Pins30
SWJ Debug Port Connection with Standard JTAG Connector30
Figure 15. JTAG Connector Implementation30
Recommendations31
Printed Circuit Board31
Component Position31
Ground and Power Supply (VSS,VDD)31
Decoupling31
Figure 16. Typical Layout for V31
DD /VSS Pair31
Other Signals32
Unused I/Os and Features32
Reference Design33
Description33
Recommended PCB Routing Guidelines for STM32H723/733, STM32H725/735 and STM32H730 Microcontrollers34
PCB Stack-Up34
Crystal Oscillator35
Power Supply Decoupling35
Figure 19. Decoupling Capacitor Placement Depending on Package Type35
Figure 20. Example of Decoupling Capacitor Placed Underneath35
High Speed Signal Layout36
SDMMC Bus Interface36
Figure 21. Microsd Card Interconnection Example36
Flexible Memory Controller (FMC) Interface37
Figure 22. SD Card Interconnection Example37
Octo-SPI Interface38
Figure 23. Octo-SPI Interconnection Example38
DFSDM Interface40
Figure 25. Stereo Microphone Interconnection40
Embedded Trace Macrocell (ETM)41
Use Case Examples42
Table 11. Use Case Examples42
Conclusion43
Revision History44
Table 4. Clock Source Generation44
Figure 3. Power Supply Component Layout44
Table of Contents45
Contents45
List of Tables48
List of Figures49

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