Supermicro X11DPU - System Block Diagram

17
Chapter 1: Introduction
Note: This is a general block diagram and may not exactly represent the features on
your motherboard. See the previous pages for the actual specications of your moth-
erboard.
Figure 1-3.
System Block Diagram
DMI
DDR4 DIMM
DMI
PE1
Upper
Upper
x4
x8
x16
x16
NIC
NCSI
Port A
x8
DDR3
VGA
UART
Port C
Port C 0~10
x8
Port B
x8
Port B
Port B 8~15
x8
NCSI
Port C
Port C 11~15
x8
Port B 0~7
Port A 0~7
port 0,1
REAR
port 3
FRONTTYPE-A
5+1 PHASE
165W
VR13
VCCP0 12v
5+1 PHASE
165W
VR13
VCCP1 12v
A
DDR4 DIMM
#1
#2
#1
#2
DDR4 DIMM DDR4 DIMM DDR4 DIMM
#1
#2
DDR4 DIMM
#1
#2#2
#1
#2
#1
DDR4 DIMM
#1
#2
DDR4 DIMM
#1
#2
DDR4 DIMM
#1
#2
B
C
D
E
F
H
J
G
#2
#1
#2
#1
K
L
M
DDR4 DIMM
#1
#2
DDR4 DIMM DDR4 DIMM
P1_NVMe1
x4
x4
x4
x4
x4
P1_NVMe2 P2_NVMe2P2_NVMe1
3bit
5bit
LAN
DDR4
VGA
PHY
RTL8211F
IPMI LAN
RJ45
BMC
AST2500
HWM
SPI COM1
32MB BMC
SPI FLASH
PE LPC/eSPI
SPI USB
32MB BIOS
SPI FLASH
MUX
TPM
Header
SPI
USB2.0 [6,7]
LPC/eSPIPE [5]
SATA Gen3 [0..3]
SATA Gen3 [4..7]
JS1
I-SATA0~3
JS2
I-SATA4~7
JS3
S-SATA0~3
x4
sSATA Gen3 [0..3]
PE [0..3]
sSATA Gen3 [4,5]
S-SATA4 S-SATA5
DMI
USB2.0 [8,9,10,12,13]
USB3.0 [1,2,3,4,6]
PCH
Lower
Lower
PE2 PE3 UPI1 UPI0
8GB/s 32GB/s 32GB/s 32GB/s
CPU 1 CPU 0
UPI
10.4G/11.2G T/s
Polarity Inversion
PE1 PE2 PE3 UPI1 UPI0
8GB/s 32GB/s 32GB/s 32GB/s
UPI
10.4G/11.2G T/s
Polarity Inversion
Ultra IO
WIO
port 4,5