SUPER 370SBA/370SBM/370SLA/370SLM User’s Manual
5-8
- The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of
AGP aperture and outside of main DRAM range (i.e., in the 640k - 1M range or above
TOM).
- The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of
AGP aperture.
- The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX
initiated AGP cycle.
PERR#
This option signals data parity errors of the PCI bus. The settings are
Enabled
or
Disabled
. Set to
Enabled
to enable the PERR# signal.
WSC# Handshake (Write Snoop Complete)
This signal is asserted active to indicate that all the snoop activity on the
CPU bus on the behalf of the last PCI-DRAM write transaction is complete
and that it is safe to send the APIC interrupt message. The settings for
this option are
Enabled
or
Disabled
. Set to
Enabled
to enable handshaking
for the WSC# signal.
USWC Write Post
The settings for this option are
Enabled
or
Disabled
. This option sets the
status of USWC (Uncacheable, Speculative, Write-Combining) posted writes
and is used to combine several partial writes to the frame buffer into a
single write in order to reduce the data bus traffic. Set to
Enabled
to
enable USWC posted writes to I/O. Set to
Disabled
to disable USWC
posted writes to I/O.
BX/GX Master Latency Timer (CLKs)
This option specifies the master latency timings (in PCI clocks) for devices
in the computer. It defines the number of PCI clocks a PCI master can
own on the bus after PCI central arbiter removes the grant signal. The
settings are
Disabled
,
32
,
64
,
96
,
128
,
160
,
192
or
224
.
Multi-Trans Timer (Clks)
This option specifies the multi-trans latency timings (in PCI clocks) for
devices in the computer. It reduces overhead switching between different
masters. The settings are
Disabled
,
32
,
64
,
96
,
128
,
160
,
192
or
224
.
PCI1 to PCI0 Access
PCI1 refers to AGP in BX and LX chipsets. PCI0 is the normal PCI bus.
Note: Normally AGP master should not access to a PCI target
. The
settings for this option are
Enabled
or
Disabled
. Set to
Enabled
to enable
access between two different PCI buses (PCI1 and PCI0).
To Next Page
Loading...
Need help?
General
