Tektronix FG 5010 User Manual

П
1
П
n
n
n
П
П
П
·
П
П
C
C
TRIGGER
SQWV
Ⓒ
PHASE
DETECTOR
LOGIC
LOCK
DETECTOR
TIMER
CHARGE
PUMP
pacitors to the next range up or down , as appropriate . The
Lock
Detector output is a
status
voltage that is first
delayed
by the Frequency Control circuit , operating in the Timer
mode . This
allows the lock
loop time to settle
down after
lock occurs , so the CPU does not indicate that a lock has
occurred
prematurely .
Phase
Detector
Logic
The
Phase
Detector
Logic
circuit
compares the
phase
and frequency of the incoming SELECTED SQWV signal
from Loop 1 with that of the incoming trigger signal from the
Trigger - Gate Input Amplifier . The output is a bipolar ECL
voltage level or pulse to the Charge Pump circuit and the
Lock Detector . The Phase Detector Logic consists of invert
er
U1310F , latches U1730A , U1730B , U1732A , and
U1732B ; OR - NOR gates U1720A , U1720B , and U1720C ;
and related components . The inner latches of the four pro
vide phase comparison , and the outer pair of the four .
( U1730A and U1732B ) do not become active until the fre
quency
ratio
is
2 : 1 or
more in
either
direction
.
MAIN
LOOP
Fig . 4-14 . Phase
Lock Loop
block
diagram
.
CPU
Theory of Operation - FG 5010
LOCK
LOOP
FILTER
OVER
-
UNDER
RANGE
DETECTOR
+
3467-20
Refer
to
Fig . 4-15 ,
which
depicts some of the
output
waveforms in the phase comparison mode . For this discus
sion , asuume that the two signals are equal in phase and
frequency , as depicted in the figure . Also assume that all
four latches have just been reset . As the first positive transi
tion occurs ( since the signals will never be precisely in
phase , assume that the trigger leads slightly ) , U1730B sets .
Neither
U1732A
nor
U1732B
will
set , since
the input
signal
has not yet arrived , and U1730A cannot set , since a low
level is at pin 7
when the trigger
arrives . The high
at pin 5 of
U1720A
enables
that
gate to
begin driving the
Charge
Pump
to increase the Main Loop frequency , and the low from pin
14 of the
latch
permits
U1730B
to
control
the
output
of
U1720B , which is still low . ( The high from U1730B pin 15 is
also applied to the D input of U1730A to arm that latch for
the next incoming trigger cycle . ) Before the circuits can real
ly begin the charge pump action , the positive edge of the
internal square - wave signal occurs , setting U1732A . The
other half , U1732B , cannot set because pin 10 is low when
the clock occurs . The set condition of U1732A causes pin 2
to go high , and pin 3 to go low . This low is applied to
U1720B pin 10 , which resets both latches and terminates
4-37

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English