Tektronix FG 5010 User Manual

Theory of
Operation - FG
5010
is
applied from Q1034
to the base
of Q1030 to
ensure fast
and positive switching of the circuit . The switching point of
the Schmitt trigger is fixed at the base of Q1030 by jumper
P1032 . Depending on the position of the jumper , the switch
ing
point is
V or
+0.5
V.
The
output of the
Schmitt
trigger is a
squarewave
signal
.
The signal is applied to buffer - inverts U1212A and U1212F
for
application
to the slope
selection
circuit . Also
from the
output of U1212F , the signal passes through R1244 to
U1730 , pin 9 ( Diagram 16 ) in the Phase - Frequency Detector
circuits
.
Trig -
Gate
Slope
Selection
The
circuit consists of three
exclusive - OR
gates
,
U1340A , U1340B , and U1340C , and pull - up resistor R1341 .
The square wave from the Trigger - Gate Input Amplifier is
applied to one input , pin 13 of U1340C . The other input , pin
12 , is
controlled by latch U1422 ,
depicted on
Diagram 17 .
When the CPU requires a plus slope , the control line is
low , and the
Schmitt Trigger
output passes
unchanged
through U1340C . For negative slope , the control line is high ,
and U1340C inverts the signal . The output signal from
U1340C is coupled to pin 5 of U1340B , a buffer that is con
nected with
U1340A
to
provide triggering and gating
from
the
CPU .
Trigger
Status
Sensor
The Trigger Status Sensor senses the status of the in
coming trigger and sends the status information to the CPU .
The circuit consists of one - shots U1630 , U1440A , and
U1440B , and
related
circuitry
.
The slope - selected trigger signal is applied to pin 5 of
U1340B , which passes the signal through R1240 to be ap
plied to the Loop 1 circuits via the Interconnect board . At
the output of U1340B , the trigger signal is joined by the μP
TRIG / GATE , inverted by U1340A and applied to the wired
OR
connector of the
two
gate
outputs .
Through
U1340A
, the CPU can
supply triggers
to Loop
1 , and by the same means , so can an external controller .
The trigger from U1340C also drives one - shots U1630
and U1440A .
The first , U1630 ,
is a pulse -
stretcher
that en
sures that all incoming triggers can be noted by the CPU .
The output pulse is applied to U1430 ( Diagram 19 ) , which
shifts it out to the CPU . Any negative pulse that is less than
1/7 second in length is stretched to that length . Diode OR
gate passes any longer pulse length . A negative edge ap
4-36
plied
to pin 5 of
U1630 causes
pin 7 and the
junction of
CR1541 and CR1540 to move low and stay low for 1/7
second . If the
applied
signal
is of longer
duration
, CR1540
holds
the
junction low even
after the
one - shot resets
.
The
trigger is also
applied
to
U1440A ,
which with
U1440B forms a frequency - sensitive pulse circuit . If triggers
occur that
are
faster than 3
Hz , the
CPU is
informed of
such
, and will flash
the front - panel
TRIG'D lamp
at a fixed
rate
. If the pulse
is
slower than 3 Hz
, the CPU
will flash the
lamp
at the
incoming
pulse
rate
, as
sensed by
U1630 .
A
negative transition at input
pin 5 of
U1440A sets the
one shot , and its output , pin 6 , stays high for 1/3 second .
The positive transition at U1440B sets that one - shot , and
its
output moves low for
1/2
second
.
Diodes CR1440 and
CR1441 form an AND gate . The output of the AND gate
stays
high if
triggers arrive
at a rate
of more than
3 Hz ,
because the output of U1440A does not go low to trigger
U1440B . At rates lower than 3 Hz , the output is a short
positive pulse that occurs for each incoming trigger . The
output level or pulse , whichever the case , is sent to U1430
for
use by
the CPU
.
16 LOCK CIRCUIT
Introduction
Theo Lock Circuit permits the FG 5010 to lock the inter
nally - produced signal on an externally - applied signal . The
actual loop consists of more than just the circuits on this
diagram ,
as
shown in Fig .
4-14
.
The major components of the Phase - lock system include
the Phase Detector Logic , Charge Pump , Lock Loop Fil
ter , Over and Under Range Detector , and Lock Detector , all
depicted on Diagram 16 , plus the Main Loop , Timer , and
CPU . The trigger is applied to the Phase Detector Logic .
This circuit produces voltage pulses that drive the Charge
Pump , which furnishes current to the Lock Loop Filter .
The DIFFERENCE VOLTAGE is summed at the loop filter
input
to permit the
CPU , through
Loop 1 , to
determine the
phase difference at which phase - lock is to occur . The cur
rent applied to the filter is integrated to produce a ramp of
varying rate and direction , depending on which of the com
pared signals leads , and by what amount of lead . The out
put is the LOCK FREQUENCY CONTROL VOLTAGE ,
which is applied to the Frequency Reference Circuits of
Loop 1 to alter the frequency of the Main Loop .
The Over and Under Range Detector determines if the
frequency range of the Main Loop is appropriate , and in
forms the CPU if it is too high or too low . The CPU responds
by changing the Main Loop and the Lock Loop Filter ca
U
U
U
U
بال
U
U

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English