Tektronix FG 5010 User Manual

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age ramp of varying rate and polarity , called LOCK FRE
QUENCY
CONTROL
VOLTAGE
.
This
signal is
applied
to
the
Loop 1
Reference
Frequency
circuits
.
The
first
of
the
two
integrators
consists of
amplifier
U1820D
,
multiplexer U1710B ,
transistors Q1626 and
Q1622
,
and
related
components
.
Using
the
capacitor
that
connects to
each of the
four
multiplexed
inputs
of
U1710B
,
the integrator produces ramps of four different rates , de
pending on the frequency range of the Main Loop . The di
rection of the
ramp is
dependent
on the
direction
of the
current at the
input node of
the
integrator
,
which is deter
mined by the Charge Pump . The DIFFERENCE VOLTAGE
Φ
from
the
>
Lock
Phase
Voltage
Generator
depicted on
Dia
gram 14 is applied through R1701 and R1815 to offset the
output voltage of the integrator ; this offset controls the
phase
difference
between the loop
signal
and
the
trigger
signal
.
Data
from
the
CPU to
control the
multiplexer
is
applied
through
Q1626
and
Q1622
,
which
operate the
control
inputs
of the
device
.
These two
inputs
select the
capacitor
that
is
in the
circuit
for each
frequency
range
.
The two
lines also
control the
selection of
capacitors in
the
second
integrator .
Capcitor selection is listed in Table 4-2 .
Table 4-2
ø LOCK LOOP FILTER CAPACITOR SELECTION
Input
Code
A B
Freq
Range
200 Hz or
less
1
200 Hz to
2
kHz
12 kHz to
200 kHz
1
1 | 200
kHz to
20
MHz
U1710B
Capacitor
C1800
C1810
C1814
C1812
U1710A
Capacitor
C1704
C1700
C1702
none
The output of
U1820D
is
applied
through R1816 to the
summing node of the
second integrator
,
consisting
of
ampli
fier
U1820C ,
multiplexer
U1710A , and
related components .
This integrator is used to filter out harmonic distortion that
arises
from
the
Charge
Pump
action
.
For
example
,
at
extremes
of
phase , the
charge
pump
pulses
are
of long du
ration , and can thus modulate the LOCK FREQUENCY
CONTROL
VOLTAGE output , and
eventually modulate the
actual Main
Loop signal ,
causing non - linear
triangles
. The
second
filter
attenuates these
harmonics .
At dc , the
gain of the
second integrator is unity
, and none
of the
capacitors
is
effective
in
the
circuit
.
As the
frequency
increases , the
gain rolls
off ,
owing to the
decreasing
capaci
tive reactance in shunt with the feedback resistor , R1818 .
With each
change
of
range
in
the Main
Loop
operating fre
Theory
of
Operation
-
FG 5010
quency
and
in the first
integrator's ramp rate ,
the
capaci
tance across U1820C is reduced in value to extend the roll
off and to
avoid
excessively
altering
the
fundamental ramp
frequency . At the
highest
range
,
note that
no
capacitor is
connected
across the
second filter ;
the gain -
bandwidth
product
of
the
amplifier is such
that no
integrating
capacitor
is
required
across
U1820C in this
operating
frequency
range . From the output of the second filter , a distortion - free
voltage is applied to the Loop 1 Reference Frequency Cir
cuits , and to the Over and Under Detector .
Over and
Under
Detector
This circuit monitors the LOCK FREQUENCY CON
TROL
VOLTAGE
from
the
ø
Lock
Loop
Filter .
The
purpose
of the circuit is to warn the CPU if the output of the filter has
gone above or below permissible extremes of voltage . The
CPU responds by switching the Main Loop and the filter to a
higher
or lower range
, as
appropriate . The circuit consists
of
comparators
U1820B
and
U1820A ,
plus
related
components
.
Resistors R1716 , R1718 , and R1714 form a resistive di
vider from ground to +12 V. The voltage at the top of
R1716 is +0.55 V , and that at the top of R1718 is +9.15 V.
The
result of the
divider
is
that a
voltage passband of ap
proximately 8.6 V lies between the switching points of
U1820A , the underrange comparator , and U1820B , the
overrange
comparator.As long
as the
LOCK FREQUEN
CY
CONTROL
VOLTAGE signal is
between the two
voltages , neither of the comparator outputs will move high .
If the signal applied crosses above or below the passband ,
the appropriate output moves high to warn the CPU that the
loop
is
out of its
operating
range
.
20 N BURST CIRCUITS
Introduction
This Diagram depicts the N Burst circuits , which count a
number
of
events
and
produce
a
stop signal
when the prop
er number is incremented ; and the Function Selector cir
cuits , through which the CPU selects one of the three
output functions , sine , triangle , or square wave . The major
circuits depicted are the Latches , the N Burst Counter , and
the Function Selector .
Latches
This circuit
consists
of
three eight - bit
serial -
parallel shift
registers ( U1401 , U1600 , and U1010 ) , connected in cas
cade to form a 24 - bit shift register . When a burst length is
selected
, the
CPU loads a
number
that
is
computed as
follows .
The maximum capacity of the N Burst Counter is 2¹6 or
65536 decimal . Since the N Burst feature allows for a maxi
4-41

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English