Tektronix FG 5010 User Manual

Theory
of
Operation - FG
5010
mum
burst of 9999
decimal , the
full counter
capacity is not
required
. Thus
,
only 15 of the
counter bits
are
controlled
by
the
latches , and
the
output
detector
limits the
counter to
4002 hexadecimal ( 16,386 decimal ) . In addition , the counter
operates
as an N
- 1
counter .
This is
because a
burst of
one
cycle is
always
generated
by the
Trig /
Gate /
Burst Logic
cir
cuits , and the counter is not used in the case of a single
cycle
burst .
Thus , if a
1400 - cycle burst
is
required , for
example , the
counter
will be
loaded with
a
count
of
1399 .
Using this
same
example
, the
CPU
loads the
latches
with
the difference ( 1686-1399 1487
) ,
so
that
when
the
counter increments to 4002 hexadecimal , 1399 cycles will
have occurred . ( The 1400th cycle occurs during the end of
burst
operation . )
=
Only
two of
the
latches are used
for the N Burst
Counter .
The third controls the Relay Drivers that select the appropri
ate function that is applied to the Output Amplifier circuits .
N Burst
Counter
The N Burst Counter produces a controlling signal ( END
OF BURST ) that informs the Main Loop that the number of
cycles required in the output signal burst will be completed
at the end of the next cycle . The counter consists of four 4
bit
binary
presettable
elements that are
connected in
cas
cade
,
configured to count no
higher than
4002
hexadecimal .
The entire counter consists of NAND gates U1510A , B , and
C , one - shots U1410A and B , and counters U1400 , U1411 ,
U1500 , and U1610 . The STROBE SS signal from the CPU
is applied to all three latches , which transfers the serially
applied
data to
the parallel outputs
of the latches
. The
STROBE SS signal is also applied to pin 9 of U1410B , so
that when the signal returns low , it triggers that one - shot ,
producing
a negative
-
going output
pulse of
about
80
ns du
ration . This pulse is applied to pin 11 of U1510C , which up
to now has a high level at all three inputs ( pin 9 is held high
by +5 V , and in quiescence , U1410A holds pin 10 high . )
The
negative
pulse
is inverted
twice through
U1510C and
U1510B , then applied to pin 4 of U1511 . If flipflop U1511 is
not set , the END OF BURST signal will be forced high . The
negative pulse is
also applied to
the load input
, pin 11 , of
each of the four counter elements , which loads the number
from the CPU ( via the latches ) into the counter . After about
80
ns , the load
inputs move
high , and
the counters
wait for
the burst cycle to begin . The trigger signal causes the loop
to begin producing the signal , and square waves are applied
to the counter from Diagram 22. When U1400 pin 2 and
4-42
U1610
pin 6
move
high (
indicating
that
the
counter
has
in
cremented to
4002
hexadecimal ) .
U1510A pin 12
moves
low
, ( pin 13
has been
high since
commencement
of count
) .
The
next positive
edge applied
to the
clock
input
clocks the
low
to the
Q
output of
U1511 ,
pulling
the
END OF
BURST
line low . The low level causes U1510A pin 13 to move low ,
pulling
U1510A pin 12
high . The
following
positive edge
of
the
applied signal
( which
is the
middle of
the last
cycle
to
be
added to the count of N - 1 ) clocks the high to the Q output
of U1511 , and the END OF BURST signal returns high .
(
Thus
, this
signal is low
only
for
the last
half
of the N
- 1
cycle
and the first
half of the last
cycle of the burst
. ) The
high
from
U1511 triggers
one - shot
U1410A , which
through
U1510C
and U1510B
loads the
next number
into the
counters and enables count . The signal also holds U1511
set for about 80 ns . This keeps the flipflop from responding
to
any
aberration
during burst
termination . This
last cycle
that
resets U1511
brings the
total to the
desired number of
cycles in
the
burst .
In the special case where a burst of one cycle is required ,
the N Burst circuits are not involved . The one cycle is gener
ated by the action of the Trig / Gate / Burst Logic circuits in
Loop One
, just
as
through Trig
mode had
been selected
.
During
operations
other
than N
Burst , the
N
Burst circuits
continue to run, but the Loop One logic ignores the END OF
BURST
line
.
Function
Selector
The Function Selector is controlled by the CPU , and se
lects
either the sine ,
square , or
triangle - wave
function
for
application
to the
Output
Amplifier . The
circuit
consists of
latch U1010 , drivers U1110A through F , and dual latching
relays
K1020 ,
K1110 , and
K1120 , plus
resistors
R1122
and
R1225 .
When
a
function is to be
selected ,
data from the
CPU is
shifted into U1010 . When the STROBE SS signal moves
high , the data is transferred to the output register , and ap
plied
to the
six drivers
. The
MAGLATCH
STROBE pulse
furnishes the current to energize the relays in the required
direction to select one of the three signals applied to the
three
relays .
The two
functions not
selected are
terminated
by 75 resistors to reduce load changes on the driving
circuits .
(
8
)
)
U
U
U
U
U
U
U
U
U

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English