Tektronix FG 5010 User Manual

Theory
of
Operation -
FG
5010
17
TRIG
17
4-60
PART
OF
U1720
TRIG
PA4
CA2
PAS
PB7
PA6
PB7
PART OF
U1720
J
ட
PA4
S
6
39 H
7
H 12
13
A ,
L
- OFF
H - ON
8 L
6
B.
L - OFF
H - ON
13
V
DETAILED DIAGRAM .
( X
DON'T
CARE
)
11
11
9
U18000
U18000
9
U1800C
U1800C
10
SIMPLIFIED SIGNAL PATH .
10
n
jumper
P1210 on Diagram
5 and is forced
low during
Kernal
testing . A low FI signal disables buffer U1330 , thus allowing
complete
ROM testing .
This
arrangement
provides
that ,
whenever
address
line
BA15 is high , the FI signal is high , and a read operation is
selected ( RD is low ) , buffer U1330 will supply the addressed
ROM or Patch EPROM data to the Microprocessor ( Dia
gram 5 ) via
the data
bus .
Thus
, the
buffer
is enabled
for
addresses in the range from 8000 through FFFF during a
read operation when the Kernel test configuration is not
selected .
L
Address
Switch
The
Address Switch circuits
consist of six
manually
oper
ated
switches that are
accessible
through
cutout
in
the
FG 5010 rear panel . These switches allow the user to as
sign the IEEE - 488 bus address of the FG 5010. All six
9
10
U1810B
U1810B
S
D
R
C
Q
D
Q
12
4 H
J
-
OFF
L
-
ON
U1800B
=
OFF
L
-
ON
12
10
10
9
Fig
. 4-23 .
Generation of gate from
IEEE - 488 <
GET >
command .
Z
-
OFF
J
- ON
U1812C
U1812C
Z
-
OFF
J
-ON
P1050-58
8
UP
TRIG
/
GATE
OUT
(
LOOP2
)
J1050
3467-29
switches are contained in switch module S1121 and are as
signed
binary
weights with
section
1
being the
least signifi
cant
. A pull - up resistor
is
connected to each line to
provide
the
proper
high -
logic
level .
The
resistors
are all
contained in
resistor pack
R1121 .
Like
ROM / Patch
EPROM buffer U1330
, tri - state
buffers
U1230 and
U1232A
operate
as
unidirectional
buffers
since
the
data
are read
from
switches . The
Address
Switch cir
cuits are
thus accessed
by the
ADDRESS
SWITCH
EN
ABLE
signal applied
to AND
- gate
U1722D from Device
Address Decoder U1520 ( Diagram 6 ) or the FI signal , also
applied
to
U1722D , from jumper
P1210 on
Diagram 5. ( The
ADDRESS SWITCH ENABLE signal occurs only in the ad
dress
range
between 2000 and
3FFF . The FI signal
is low
only during Kernel testing and causes the Microprocessor to
read the Address Switch output at all addresses . ) From
U1722D , the output is applied to OR - gate U1612A along
with the RD signal from the Read / Write Control Logic on
U
U
U
U
U
U
U

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English