Tektronix FG 5010 User Manual

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-
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C
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M
DO
П
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17
TRIG
17
PART OF
U1720
PA4
CA2
PAS
PB7
PA6
PB7
X
PART OF
U1720
PA4
CA2
6
H - ON
39 u
7
8
L - OFF
6
39
L
A.
DETAILED
DIAGRAM .
DON'T
CARE )
L
(
X
12
13
✔
L
-
OFF
H - ON
u
8
9
11
U1800C
H
U1800D
U1800C
B.
SIMPLIFIED SIGNAL
PATH
.
10
♫
10 11
Patch
EPROM
U1640
provides for
programming
flexibil
ity . When
the data in a
particular ROM
address must be
changed
, the
new data
can be
programmed into
the Patch
EPROM
and
substituted
whenever the
no -
longer
-
valid
ad
dress
is
selected .
Addresses to
be
patched are
detected by
Field
Programmable
Logic
Array
(
FPLA )
U1420 (
Diagram 6 ) .
When
a
ROM
address for
which
the
data were
modified
is
detected by the
FPLA
, its
FLAG
output
becomes low ,
which
disables
Address
Line
Buffer U1312
and
Address
Decoder
U1520 ( both on Diagram 6 ) and enables Patch EPROM
U1640
.
At the
same
time
,
the
FPLA
function
outputs ( FO
through F7 ) become active and supply address bits BA3
through
BA10
, which are
normally provided by the
Micro
processor via buffer U1312 . Address lines BAO , BA1 , and
BA2 are
provided
by
the
Microprocessor as
usual . This
ar
rangement maps in eight - byte blocks of the Patch EPROM
data
whenever
address
lines
A3
through
A15
equal
one
of
the addresses programmed into the FPLA .
10
Note that for the
FPLA
to
detect an
address , both
the
VMA
signal
from
the
Microprocessor
(
Diagram
5
) and the
ROMDIS signal from
the
service
interconnect
connector
U1810B
> C
U1810B
R
5
lo
12
Q
12
4 H
U1800B
J
-
OFF
L
-
ON
J -
OFF
I
-ON
10
10
9
U1812C
Z
OFF
J
- ON
Theory of Operation - FG 5010
U18120
-OFF
I
-
ON
P1050-5B
up
TRIG
/
Fig . 4-22 .
Generation
of gate
from front panel or
GATE ON / GATE
OFF
command .
GATE
OUT
( LOOP2 )
J1050
3467-28
( also on Diagram 5 ) must be high , and the Normal / Disable
Patch jumper
on
Diagram
6
must be in the
Normal
position
.
When patching occurs , substitute data bytes are read onto
the data bus just as ordinary ROM data would be . Address
es for the
Patch
EPROM
,
when
not
selected by the
FPLA
,
are in the
range from
9800
through 9FFF .
Tri -
state
data bus
buffer
U1330
operates as
a uni
directional
buffer
since
its
data are
from
read
-
only
memo
ries . It
is
enabled
only during a
read cycle by the
RD
signal
from
the
Read
/
Write
Control
Logic (
Diagram
5 )
being ap
plied as
one of the
two
enable
signals
.
This
provides that
there will be no possibility of bus contention by the ROM
circuits
. (
Since the
ROMs
are
addressed
during
either
a
read or a
write
operation
,
ROM data
are
present at the
U1330 buffer input ; but
the
disabled buffer
prevents
these
data
from
reaching
the
bus
. )
The
second
enable for the
buffer
is
the FI
signal
applied
through NAND - gate U1730D in combination with buffered
address bit
BA15
.
The FI
signal
(
Forced Instruction ) is
from
4-59

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English