Tektronix FG 5010 User Manual

Maintenance - FG
5010
FG
5010
POWER - ON
SELF
TEST
ERROR
CODES and
DESCRIPTION
The
FG
5010
begins the
self
test routine by
illuminating all
front panel indicators .
The Loop 1 board is placed in the triggered mode during
these tests . The manual trigger signal is held asserted by
the MPU to prevent triggering the main loop . The high fre
quency
square (
HFSQ )
signal
from
Loop 1
should be high
in
this mode . If , for any reason , the HFSQ signal ( U1232 , pin
14 , Loop 2 ) is not a steady high , the frequency control logic
test will fail , displaying Error 323. For example , a failure in
one of the 12 V supplies can cause Error 323 .
Errors 340 , 341 , 350. The internal RAM in the 6802 MPU
chip ( U1310 ) is tested . Error 350 is displayed if a fault is
found
.
The next
RAM
tested
is
the
1024 by 8 bit
RAM
on
the CPU
board
.
Error 340
indicates
a
U1400
failure
, and
Error 341
indicates
a
U1500 failure .
Errors 370 , 372 , 374 , 390 , 392 , 394. The next test per
formed is ROM placement . Errors 370 , 372 , and 374 indi
cate that U1540 , U1440 , or U1332 sockets contain the
wrong
ROMS , respectively
. Next , the
ROMs are tested
for
correct checksums . Errors 390 , 392 , or 394 indicate that
U1540 , U1440 , or U1332 ROMs contain incorrect data , re
spectively . If a ROM or RAM fault is detected , the MPU
halts program execution , i.e. , the instrument ignores all in
put from the front panel or the IEEE - 488 bus . The MPU then
begins execution of a program loop that exercises the RAM
chip
select and
read / write
signals
.
This
program loop re
sides at addresses E97A through E987 . First , a hex 55 is
written to location 0555 ( hex ) . Then , data is read from loca
tion 0555 and
the
complement of the
response
is
written
back to location 0555. This inverted pattern is then read
from location 0555. The GPIB address switch is then read
to provide a chip select pulse on test point 1331. This pro
gram is executed repetitively so that an oscilloscope may be
used to troubleshoot RAM problems . Use TP1331 as an
oscilloscope trigger signal . Note that the instrument will ig
nore all input from the front panel or the IEEE - 488 bus dur
ing
execution
of this
program
loop
.
Errors 320 ,
321. The VIA
(
versatile
interface
adapter
)
chip ( U1720 ) on the CPU board is tested for functional timer
counters . Error 320 indicates a faulty VIA chip . The manual
trigger control logic is tested by exercising U1720 pins 6 , 39 ,
and 8. The trigger control signal is fed back to the MPU
through U1720 pin 17. Error 321 is displayed if a fault is
found .
Errors 320 , 321. The VIA ( versatile interface adapter )
chip
( U1720 ) on
the CPU board
is tested for
functional timer
counters . Error 320 indicates a faulty VIA chip . The manual
trigger control logic is tested by exercising U1720 pins 6 , 39 ,
and 8. The trigger control signal is fed back to the MPU
through U1720 pin 17. Error 321 is displayed if a fault is
found
.
Errors 322 , 323 , 324. The next area to be tested is the
frequency control logic on the Loop 2 board . All feedback to
the MPU , during these tests , is through the status shift reg
ister ( U1430 , Loop 2 ) . Do not rule out this register while
troubleshooting .
7-12
The frequency control logic is clocked by the MPU by
exercising exclusive - or gate U1340 , pin 9 , on Loop 2. The
frequency prescaler counter ( U1232 , Loop 2 ) is set to divide
by 1 , by setting U1212 pin 11 low . This should cause a high
on U1340 pin 10 .
The
test begins
by setting
U1212 pin 3 low
, to set refer
ence
frequency
counters
U1320 and
U1322 .
This also
resets flipflop U1220B . U1220 pin 8 is tested for a logic
high . Error 323 is displayed if it is low . When U1220 pin 9 is
low , the loop cycle counters ( U1130 , U1132 , U1110 , and
U1120 ) are forced to load present data provided by shift
registers U1122 and U1112 . These shift registers are set for
all
zeros ,
causing
terminal
count gate
U1230 pin 6 to
be
high . This signal resets flipflop U1220 pin 12 through gate
U1222A . U1220 pin 13 is tested for a high , causing Error
323 if low . U1210 pin 8 and U1322 pin 12 must both be low ,
or
Error
323 is
displayed
.
The reference frequency counters U1320 and U1322 are
read
through shift
registers
U1330 and
U1332 and
tested
for a count of zero ; Error 322 is displayed if they are not .
Then , the loop cycle counter present data is set to a count
of 2. This is loaded into the loop cycle counters , causing
terminal count gate U1230 pin 6 to go low and removing the
reset from flip flop U1220A . U1212 pin 3 is then set high ,
removing the reset from the reference frequency counters ,
and clocking U1220A to set pin 12 high . U1220 pin 13 is
checked for a low , causing Error 323 if it is high .
The reference frequency counter is again tested for zero ,
causing Error 322 if it is not . This indicates a problem with
reference
frequency gate
U1222D .
U1220B is
clocked by
setting
U1340 pin 9 low
. Note that
U1220B
is not
clocked
unless the clock multiplexer gate U1210B has a high on pin
4 , and U1222B has a low on pin 5. U1220 , pin 8 is tested for
a low , causing Error 323 if it is high .
The loop cycle counter is clocked from 2 to 1 by setting
U1340
pin 9 high
. Then , U1220
pins 8 and 13 must
both be
low , or Error 324 is displayed . This error indicates a problem
with
the loop cycle
counter or
terminal
count
gate ,
U1230A
.
U1220B is clocked by setting U1340 pin 9 low . U1220 pin 8
REV JAN 1982
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Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English