Tektronix FG 5010 User Manual

7
n
7
П
П
П
C
Down
Shrink Current
Source
This circuit is
also a
voltage
to
current
converter that
provides the Down Shrink Current for the Level Detector .
The stage consists of amplifier U1641D , Darlington transis
tor
Q1551 ,
transistor
Q1242
,
and
related
components . Bias
for
Q1242 is
provided by
VR1351 ,
depicted on
Diagram
12 .
This
sets
the
base
of
Q1242
at
approximately
-5.8
V.
The voltage from U1641C is applied to R1652 and alge
braically summed with the +10 V reference . The difference
drives U1641D , which in turn drives Q1551 and Q1242 . The
cascode configuration decouples the transitions from the
Level
Detector
from
affecting the
performance
of this
stage
.
Relay
Drivers
Relays K1131 through K1331 are driven by buffers
U1311
through
U1411
.
These
drivers are
Darlington pairs
,
one pair to each driver . Each is in turn driven by a line from
one of the
latches . The
purpose
of each
relay is stated
in
Table 4-1 .
K1131A
K1131B
K1231A
K1231B
K1321A
K1321B
K1322A
K1322B
K1323A
K1323B
K1331A
K1331B
Table 4-1
LOOP 1 MAGLATCH RELAYS
Selects low -
frequency triangle .
NC
Selects
high -
frequency
triangle .
Connects 75
load to
Triangle
Buffer
.
Connects
loop
capacitor C1411 into loop .
NC
(
a )
Connects loop
capacitor
C1211 into loop .
Inhibits
shrink
control
operation
.
Connects
loop
capacitor
C1421
into loop .
Selects shrink
control
resistance
.
Conencts
loop
capacitor
C1422
into loop .
Selects
shrink
control
resistance
.
Strobed +8 V is
applied
to
P1510
, pin
8A ,
which pro
vides
the
current path
for the
relays
to
energize
.
( The
emitters of the Darlington buffers are connected to the
+8 V
return
line
. )
Once a
driver has
energized , a
relay
through the A coil , for example , the relay will stay latched
until the opposite driver pulls the relay contact to the B side .
Note
that
K1331
,
K1323
,
K1322
, and
K1321 are
individually
controllable , and that K1231 and K1131 are cross - connect
ed . The
first four
control
the
loop
timing
capacitors , as
noted
in Table 4-1 . The remaining two are cross - connected to en
sure that these two relays are mutually exclusive ; i.e. , the
two triangle signal sources are never connected again .
Theory of
Operation
- FG
5010
14 CLAMP CIRCUITS
国
Introduction
Refer to Fig
. 4-9 ,
which
is a block
diagram of the
Clamp
Circuits . The
TRIG / GATE ,
FREEGATE
,
BURST , END OF
BURST
,
and
HFSQ
signals
are
applied to the Trig
/
Gate / Burst Logic
Circuit . This is
the mode logic
that deter
mines the
Clamp Enable
Switch action and
timing . The
FREEGATE and
BURST
signals
set
the modes ,
and the
other signals provide the timing for the events from the cir
cuit . The
logic
circuit also
ensures that the
main loop
re
mains running during Loop 2 operations to furnish the
triangle and square waves to the Loop 2 circuits .
The Square Selector receives the HFSQ , HFSQ , Low
frequency squarewave , and data signals , and produces the
output selected squarewave signals . The selection is con
trolled by the HI RANGE input line .
Latch
U1141 receives ,
stores and
applies
the
digital
data
that
controls > DAC
U1041
-
U1042A
.
This
circuit
produces
an output voltage that is a function of the input data and the
+10 V reference . This voltage is applied to two networks
that establish a difference between the +10 V reference
and the applied voltage . The difference is derived by two
separate summing networks , each of which supplies an am
plifier . These are the ø Lock Phase Voltage Generator and
the Clamp Phase Voltage Generator . The first of the two
produces a voltage that is applied to the Loop 2 circuits to
determine the
relative
phase
between
the FG
5010
output
signal and the input signal during phase - lock operation .
The
Clamp
Phase
Voltage Generator , which
is gated by
the Clamp Enable Switch , is used during the modes where
the loop is controlled externally ; i.e. , gated , triggered , and
burst modes . The stage sets the point at which the loop will
be stopped , due to the data applied from U1141 .
The Clamp Enable Switch is driven by the logic circuits ,
discussed later . The switch steers current from the Clamp
Phase Voltage Generator circuit to permit free - running the
main loop , or clamps the loop by shutting off the current
path . The circuit also enables or disables the Schmitt Defeat
gate , which
does not
operate
during
clamp
operations
.
$
DAC
The DAC
produces an
output
voltage
that
is a pro
grammed fraction of the +10 V reference . The circuit con
sists of DAC U1041 , amplifier U1042A , and related circuitry .
Feedback current for the amplifier is through the internal
feedback resistance in U1041 .
4-17

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English