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Tektronix FG 5010 User Manual

Tektronix FG 5010
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n
П
П
1
П
1
1
C
C
C
Refer
to
Fig
.
4-10
,
which
is
a
simplified
diagram
of
the
Phase
Clamp
Circuits
.
Assume
that
transistor
Q1224
on
Diagram
14
is
conduct
ing
.
This
indicates
that
the
main
loop
is
in
a
free
-
running
mode
,
and
no
gating
requirements
exist
.
The
collector
of
Q1224
is
at
+1.4
V
,
clamped
at
that
point
by
CR1322
and
CR1321
.
All
of
the
current
through
Q1235
flows
through
Q1224
,
since
CR1323
is
back
-
biased
.
Phase
Clamp
Diode
CR1324
is
also
back
-
biased
,
so
no
current
passes
through
that
diode
.
Current
through
Q1225
passes
through
R1126
,
since
CR1323
is
reverse
-
biased
by
the
+1.4
V
clamping
potential
.
Next
,
assume
that
the
Trig
/
Gate
/
Burst
Logic
circuits
re
ceive
instructions
to
operate
in
one
of
those
three
modes
.
The
Clamp
Enable
Switch
is
tripped
,
and
Q1224
is
cut
off
.
The
node
at
the
cathode
of
CR1324
drops
to
the
point
where
CR1323
and
CR1324
each
take
part
of
the
current
through
Q1235
.
Both
diodes
are
conducting
since
I
is
UP
through
CR1324
and
21
,
is
through
Q1235
,
then
I
must
also
flow
through
CR1323
,
and
the
anodes
are
at
the
same
potential
.
Thus
,
the
voltage
at
the
emitter
of
Q1225
,
which
is
the
phase
clamp
voltage
,
is
also
the
voltage
at
the
loop
+
10.0V
REF
DATA
8
1
BIT
PHASE
DAC
Theory
of
Operation
-
FG
5010
capacitor
circuit
.
In
this
way
,
the
DAC
controls
the
loop
capacitor
in
gated
,
burst
,
and
triggered
modes
.
V
UP
FROM
SYM
SECTION
Clamp
Offset
adjustment
R1151
is
set
for
a
-1
V
trip
point
at
pin
4
of
u1351A
,
the
Level
Detector
,
with
the
DAC
set
to
zero
data
(
-90
°
)
.
Clamp
Gain
adjustment
is
set
for
+1
V
at
the
same
point
with
the
DAC
set
for
255
decimal
(
+
90
°
)
.
Trig
/
Gate
/
Burst
Logic
Circuits
Refer
to
Fig
.
4-11
,
which
is
a
simplified
diagram
of
the
logic
circuits
.
Also
refer
to
Diagram
14
while
reading
the
description
.
The
circuit
consists
of
gates
U1211A
,
U1211B
,
U1011D
and
U1211C
;
dual
flip
-
flop
U1201
;
transistors
Q1102
,
Q1201
,
Q1114
,
and
Q1113
,
plus
related
compo
nents
.
The
logic
circuit
provides
the
gating
and
triggering
control
over
the
phase
clamp
circuits
during
gating
,
trigger
ing
,
and
burst
modes
.
The
FREEGATE
signal
from
latch
U1301
is
applied
to
Q1102
,
the
emitter
of
which
controls
one
input
of
U1211A
.
When
FREEGATE
is
high
,
the
triggers
and
gates
are
DIFFERENTIAL
DRIVE
FROM
U1211C
Q1224
I
UP
+
12V
1
UP
3000
2
1
UP
Fig
.
4-10
.
Simplified
diagram
of
Clamp
Phase
Circuits
.
Q1223
+
1.4V
E
CLAMP
LOOP
CAP
3467-17
4-19

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Tektronix FG 5010 Specifications

General IconGeneral
BrandTektronix
ModelFG 5010
CategoryPortable Generator
LanguageEnglish

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