Tektronix FG 5010 User Manual

Theory
of
Operation -
FG 5010
VARIABLE
SYMMETRY
AND
INTEGRAL
CYCLE
COUNTER
Introduction
The circuits depicted on Diagram 17 make up two major
circuits : the
integral Cycle
Counter and
the
Variable Sym
metry
Counter
.
The
integral
Cycle Counter
keeps track of
the
output of
the Variable Symmetry Counter to be sure that if it is gated ,
the
number of
cycles
counted is in
multiples of 2000
.
The Variable Symmetry Counter divides the incoming
squarewave by
the
symmetry
factor that
is
applied by
the
CPU . The output of the counter , applied to the Integral Cy
cle Counter and LF Generator Counter , is a squarewave
that
is one
frequency
for 1000
cycles ,
and
another in the
next 1000 , unless 50 % symmetry is selected . In that case ,
the
frequency is
the same for each
group of 2000
.
Variable Symmetry Counter
This circuit consists of a cascoded pair of synchronous
four - bit counters ( U1432 and U1530 ) , one - shot U1202 ,
NOR gate U1300A , and latches U1520 and U1620 . ( The
relationship
of the
latches
to the
CPU
has
been discussed
earlier in the Digital Control circuits discussion . )
In generation of a single low - frequency triangle cycle ,
1000 increments are always used in the up slope and 1000
in
the down slope
. Since the number
of increments
on each
slope is constant and the symmetry varies from 10 to 90 % ,
the number of cycles per slope must change to match the
symmetry
.
Thus
, for
example
, if the
up
symmetry is 20
%
and the down symmetry is 80 % , the divisor for the up slope
to
the
Variable Symmetry
Counter will be
set by the CPU
to
be 20 , and 80 for the down slope . Therefore , the frequency
applied to the
Symmetry
Counter must
be
100,000 times
the
desired
output
frequency .
At the beginning of each up slope , U1620 loads the up
slope
symmetry
factor into
U1432 and
U1530 .
This is illus
trated by the following example . Assume that the symmetry
is to be 45 % -55 % . The counter capacity is 256 , so U1620
loads 256-45 = 211 into the counter . At the beginning of
the
down slope
, U1520 is ready
to load
256–55 = 201 into
the same two counters . This operation switches back and
forth so long as the 45-55 symmetry is required , and a sig
nal is to be generated . The counter is reset in two ways : 1 )
the
ripple carry from
U1530 moves
high when the
counter
overflows ,
causing
U1300A to reset both
U1432 and
4-24
U1530 ; 2 ) the
CPU
generates a
signal through U1402B
that
resets
the
counter before
beginning a
different symmetry
or
at
the
outset of
count . This
reset signal is also
sent to
the
LF
Generator
Counter
on Diagram
18 to reset
that
counter .
The
output of the
Variable
Symmetry
Counter is first
fed
through one
- shot
U1202 , which
widens the
output
pulses
for
use by other
circuits
.
The
output is fed to the
Integral
Cycle Counter and to the LF Generator Counter , depicted
on
Diagram
18 .
Integral
Cycle
Counter
The
Integral
Cycle
Counter
accumulates the
output of the
Variable
Symmetry
Counter to
determine if the
total
count is
2000
, and
causes the
Variable
Symmetry
Counter to
reload
at
the
completion of each
2000
count
. The
stage consists of
up - down counters U1200 , U1102 , U1100 , gates U1312B ,
U1312C
, U1312A
,
inverters
U1310E
and U1310A
, flip - flop
U1402B , and
related
components
.
At the outset , the load input of each counter is pulled low
by
the CPU by
way of U1422
pin 11 , through
U1312C
.
When the CLOXON signal from Loop 1 is asserted ,
U1402B is set . CR1410 allows the CPU to reset when re
quired
. The low
level from pin
8 of
U1402B
is
applied to pin
13 of U1312B and pin 3 of U1300A , which permits other
inputs to exercise control of these two gates . The pin 9
output of
U1402B
presets the LF
Generator
Counter depict
ed on Diagram 18. Since pin 2 of U1312B is also low ( this
line is asserrted when the HOLD function is activated ) , the
HF
SQWV signal
passes through
U1312B . The
signal is
di
vided by the symmetry factor , then passed to the Integral
Cycle Counter . When 2000 events have accumulated in the
counter , all three inputs to U1312A are low , causing a posi
tive
edge to be
applied to
the
clock input , pin
11 , of
U1402B
.
If CLOXON is not low yet , the edge is ignored by U1402B .
The
same event
is
passed
through U1312C
to reset and
reload the
Integral
Cycle Counter
.
When CLOXON
eventual
ly goes low , U1402B is reset by the very next positive edge
from
U1312A at
the end of the next
2000 count cycle
. When
U1402B
resets , the
Variable Symmetry
Counter
is reloaded
by U1300A , and the high at pin 13 of U1312B prevents
further
passage of the
squarewave
.
"
The
third input
to
U1312B ( pin
2 ) comes
from the
CPU
via
U1510
.
This line is
asserted when
the
HOLD function
is
activated
. It
permits the
signal to
be
stopped and
held
indefi
nitely at
any point on
the
output
waveform
.
This
only ap
plies
,
however , to
signals
generated in Loop
2.
When pin 2
is
released
, the
cycle continues
until
otherwise
terminated
by normal means .
(
8
)
U
U
U
U
U
U
U
U
U

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English