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Tektronix FG 5010

Tektronix FG 5010
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18
LOW
FREQUENCY
GENERATOR
Introduction
The
Low
-
Frequency
Generator
receives
the
output
of
the
Variable
Symmetry
Counter
,
adds
the
phase
information
from
the
CPU
,
and
produces
the
low
-
frequency
squarewave
and
triangle
-
wave
signals
for
use
in
the
Output
Amplifier
.
The
circuits
consist
of
the
LF
Generator
Counter
,
the
Max
Min
Count
Detector
,
the
LF
Triangle
DAC
,
and
the
LF
Trian
gle
Buffer
.
LF
Generator
Counter
This
circuit
consists
of
latches
U1510
and
U1420
,
and
synchronous
up
-
down
counters
U1410
,
U1412
,
and
U1500
.
Refer
to
the
Digital
Control
circuits
discussion
just
following
the
Loop
2
Block
Diagram
Description
for
the
description
of
how
the
CPU
and
latches
operate
here
.
At
the
time
that
the
Variable
Symmetry
Counter
is
loaded
by
command
of
U1402B
(
Diagram
17
)
,
that
same
flip
-
flop
pulls
high
on
the
load
input
(
pin
11
)
to
each
of
the
counter
elements
(
U1500
,
U1412
,
and
U1410
)
.
The
CPU
has
al
ready
loaded
latches
U1420
and
U1510
with
the
phase
data
,
so
the
counter
is
preset
with
a
number
that
corre
sponds
to
a
point
on
the
output
triangle
,
to
be
the
starting
point
on
the
output
waveform
.
At
the
same
time
that
the
LF
Generator
Counter
is
being
preset
,
the
CPU
commands
the
counter
to
count
down
.
This
is
by
way
of
U1402B
pin
8
on
Diagram
17
,
which
pulls
high
on
pin
5
of
U1300D
(
Diagram
18
)
,
which
in
turn
resets
U1402A
.
When
the
signal
from
the
Variable
Symmetry
Counter
arrives
at
the
clock
input
of
U1410
,
U1412
,
and
U1500
,
the
counters
increment
.
The
output
of
these
counters
is
fed
to
the
LF
Triangle
DAC
for
analog
conversion
,
and
to
the
Max
Min
Count
Detector
.
This
output
counts
up
to
the
1000
count
,
decrements
to
zero
,
increments
to
1000
,
etc.
,
so
long
as
the
signal
continues
from
the
Variable
Symmetry
Counter
.
Max
-
Min
Count
Detector
This
circuit
monitors
the
LF
Genertor
Output
and
switch
es
the
direction
of
the
counters
after
each
1000
events
oc
cur
.
The
circuit
also
produces
the
LOW
FREQ
SQWV
and
LF
SQWV
signals
that
are
applied
to
U1620
and
U1520
(
Diagram
17
)
to
alternately
enable
those
latches
.
LOW
FREQ
SQWV
is
also
sent
to
U1210D
(
Diagram
19
)
to
be
applied
to
the
Loop
Cycle
Counter
,
and
LOW
FREQ
SQWV
is
sent
off
the
board
for
use
by
the
Loop
1
circuits
.
The
circuit
consists
of
gates
U1230B
,
U1300B
,
C
and
D
,
U1302
,
latch
U1402A
,
and
inverter
U1310D
.
(
8
)
At
the
beginning
of
an
operation
,
the
CPU
resets
U1402A
by
resetting
U1402B
on
Diagram
17.
This
signal
is
passed
through
U1300D
to
the
reset
input
of
U1402A
,
which
resets
and
directs
the
LF
Generator
Counter
to
count
down
.
Note
that
the
counter
always
starts
a
cycle
on
the
down
count
unless
it
is
coming
out
of
the
HOLD
function
.
Theory
of
Operation
-
FG
5010
When
the
count
reaches
,
the
pin
12
output
of
all
three
counters
causes
U1230B
to
clock
U1402A
to
the
set
state
,
which
directs
the
counters
to
increment
.
The
counter
incre
ments
to
1000
,
and
the
output
decoder
produces
the
low
level
that
once
again
reverses
U1402A
;
this
continues
as
long
as
the
counter
receives
events
from
the
Variable
Sym
metry
Counter
.
The
output
of
the
stage
is
applied
to
the
LF
Triangle
DAC
.
LF
Triangle
DAC
This
circuit
converts
the
digital
information
from
the
LF
Generator
Counter
into
a
dc
voltage
that
is
inversely
propor
tional
to
the
input
.
The
circuit
consists
of
reference
amplifier
U1502A
,
DAC
U1400
,
amplifier
U1512
,
and
related
compo
nents
.
The
reference
voltage
for
the
stage
is
set
by
VR1610
,
R1615
,
and
R1620
which
set
the
input
voltage
to
unity
-
gain
amplifier
U1502A
at
+9
V.
The
output
voltage
is
-9
V
,
which
is
applied
to
summing
resistors
R1600
and
R1503
,
Zero
Set
R1600
is
adjusted
for
1
V
when
the
DAC
input
is
decimal
1000
,
and
for
minimum
sine
distortion
when
the
loop
is
running
.
Refer
to
Fig
.
4-13
.
The
starting
point
on
the
actual
trian
gle
wave
signal
is
always
on
the
up
-
slope
for
either
Loop
1
or
Loop
2
signals
.
Thus
,
the
equivalent
of
the
positive
peak
is
from
the
LF
Generator
Counter
,
and
that
of
the
negative
peak
is
decimal
1000.
The
digital
data
thus
imposed
at
the
input
of
the
DAC
is
subtractive
,
in
that
the
larger
the
number
at
the
input
,
the
more
is
subtracted
from
the
applied
refer
ence
current
.
The
resulting
output
is
a
triangle
wave
that
varies
from
-
1
V
when
decimal
1000
is
applied
to
the
DAC
to
+1
when
is
applied
to
the
DAC
.
The
output
triangle
from
U1512
is
applied
to
the
LF
Triangle
Buffer
.
-IV
1000
COUNT
+
1V
Ø
COUNT
-
1
V
1000
COUNT
+
1V
COUNT
3467-19
ig
.
4-13
.
Relationship
of
output
triangle
voltage
to
LF
gener
ator
count
.
4-25

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