Tektronix FG 5010 User Manual

Theory of
Operation
- FG
5010
LF
Triangle
Buffer
This stage isolates the output of the LF Triangle DAC
from the load of the driven circuits . The buffer consists of
amplifier U1502B , transistors Q1624 and Q1620 , plus relat
ed components . The applied signal amplitude is adjusted by
Amplitude Set control R1500 for +1 V output when the LF
Triangle Counter is at 0. The signal is fed into the non - invert
ing input of U1502B , which forms a unity - gain buffer with
Q1624 and Q1620 . These two transistors form a current
switch for the output signal . Diodes CR1620 and CR1621
provide
bias during
crossover of
the stage . The
LOW FRE
QUENCY TRIANGLE signal is fed off the board to the Loop
1 Triangle Selector circuit for eventual use in the Sine Shap
er
circuits
.
19
FREQUENCY CONTROL
Introduction
The circuits
depicted
on
Diagram
19
compare the output
signal against a crystal - controlled standard , and report the
status of that comparison to the CPU . The major ciruits
include the Latches , the 4 MHz Clock Shaper and Gate , the
Reference Counter , the Loop Frequency Sample Status cir
cuit , the Frequency Control Count Logic , the Count Gate
Control , the Loop Cycle Counter , and the Decade Divider .
The Frequency Control also functions in an auxiliary
mode
, in
that it is
used as a
timer
during
phase
-
lock oper
ations . The timer holds off any in - lock decision until the
phase - lock circuits have had time to settle on the external
signal .
The Latches , U1122 and U1112 , are devoted exclusively
to carrying the data from the CPU to the Loop Cycle
Counter . For more details , refer to the Digital Control de
scription just following the Block Diagram Description .
Overall operation of the Frequency Control Circuits is as
follows : The Latches set a number from the CPU into the
Loop Cycle
Counter
. The
HF
square
-
wave signal
is the
counted event , and the Loop Cycle Counter is decremented
to zero by that signal . At the same time that the Loop Cycle
Counter starts , the 4 MHz signal is applied to the Reference
Counter
. When
the Loop
Cycle
Counter
reaches
zero , it
resets the
Count Gate
Control
, which
stops the 4 MHz
sig
nal . The number of 4 MHz events in the Reference Counter
is sent to the
CPU via the
Loop
Frequency
Sample Status
Circuits . Knowing the number of loop cycle events that
decremented the Loop Cycle Counter to zero , and the num
ber of 4 MHz events incremented by the Reference Counter ,
the CPU can calculate the period and frequency of the
square - wave signal , and take action to correct any
inaccuracy
.
4-26
Overall
operation of the Phase
- lock Delay
function
is as
follows
: The latches
set a number
from the
CPU into the
Loop
Cycle
Counter , the square
- wave signal
from the Dec
ade Divider is the decrementing event , and the counter
decrements to zero . This action is initiated by the in - lock
signal from the Phase - lock circuits . At the end of this period ,
the CPU is informed that the delay is ended , and it may now
look at the phase - lock signal . During this operation , should
the Phase - lock
circuits lose the
signal lock
altogether
, the
operation is immediately terminated . Also during this oper
ation , the Reference Counter is disabled from counting the
4
MHz
signal
.
Decade
Divider
This circuit consists of controllable decade counter
U1232 , gates and inverters U1340C , U1210B , U1310C ,
U1210D , and U1222B , plus related components . The FAST
SQWV signal from Loop 1 is applied to pins 14 and 7 of
U1232 . The control signal from latch U1510 is applied
through U1212E to U1232 to determine if the counter will
divide by one or ten . This is simply a function of the applied
frequency ; if the frequency is above 2 MHz , the signal is
divided by ten . Otherwise , the signal is passed through
undivided . The signal from output pin 11 is passed through
U1340C , which inverts the signal on command from the
CPU . Inversion occurs to allow the most favorable setup
time for the Loop Cycle Counter when the signal is
unsymmetrical . From U1340C , the high - frequency signal is
applied to a gate matrix that is controlled by Latch U1422 at
U1310C pin 7 and U1210D pin 12. This circuit determines
whether
the
high -
frequency or the low -
frequency
square
wave signal is to be applied to the Loop Cycle Counter .
Loop
Cycle
Counter
The Loop Cycle Counter consists of four 4 - bit synchro
nous
,
presettable up / down
counters that are
connected in
cascade , plus AND gate U1230A . The counters are loaded
by the latches , and controlled by the Frequency Control
Count Logic and Count Gate Control circuits . Operation of
the Loop Cycle Counter is discussed with the Frequency
Control Count Logic circuits .
4 MHz Clock Shaper and Gate
This circuit consists of NOR Gate U1222D , transistors
Q1140
and
Q1142
,
plus
related
components . The
purpose
of the circuit is to shape , level - shift , and gate the incoming
4
MHz
signal .
The crystal - controlled 4 MHz clock signal from the CPU
is applied through P1660 to the base of Q1140 , which with
Q1142 forms a differential pair . The circuit produces a signal
that is TTL - compatible and has faster transitions . From the
collector of Q1142 , the output signal is applied to U1222D ,
pin 11. The other input to the gate is controlled by the Count
@
U
U
U
U
U
U
LS
U
U

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English