Tektronix FG 5010 User Manual

7
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C
Gate
Control
circuit ,
which
controls
the
length
of
time
that
the 4
MHz
signal
is
permitted to
pass
through
U1222D .
From this gate , the signal is applied to the Reference
Counter .
Reference Counter
The
Reference
Counter
consists
of
counters
U1320
and
U1322
,
connected
in
cascade
to
accommodate a
total of
65,536
events before
overflowing
. (
The
normal
number
of
counts
for a
correct
frequency
is
about
20,000
. )
The
counter
is reset by
U1212B
, the
output of which
is high before
a loop
cycle count operation begins . The Reference Counter is also
held reset
during
phase
- lock delay
operations . The
signal
that
increments the
Reference
Counter
is the
gated 4 MHz
signal
from U1222D . The
Reference
Counter
output is fed
in
parallel to the
Loop
Frequency Sample
Status circuit for
transmission to the
CPU .
Loop
Frequency
Sample Status
Circuit
This
circuit consists of
three parallel -
serial shift
registers
that are cascade - connected , U1330 , U1332 , and U1430 .
The purpose of these registers is to convey status informa
tion to the CPU , as follows : U1330 and U1332 are dedi
cated to carrying the output of the Reference Counter , save
the
overflow line , pin 12 of
U1322 . The
data carried by
U1430 is
miscellaneous status
information :
Pin 4 -
Trigger
Status
information from the
Trigger
circuits .
Pin 5 -
Trigger
Status
information from the
Trigger
circuits
.
Pin 6 -
Frequency
under
range from
Diagram
16 .
Pin 7 -
Frequency over
range from
Diagram 16 .
Pin 1 -
Reference
Counter
overflow
in
Frequency
Control
mode .
Pin
14
-
Phase
-
Lock
Detector
output .
Pin 15
-
Loop
Counter is
running .
Pin 13 -
Loop
Counter is
ready to run .
When
the
CPU is
ready
to
interrogate the
circuit
, the
STROBE
LOOP
2
STATUS
signal is
asserted , then
the
SHIFT CLOCK signal shifts the 24 - bit word into the CPU
circuits
from
the
registers .
Frequency Control Count Logic
This
circuit includes
U1210C ,
U1310B
,
U1212B
,
U1212C , U1222C , U1222A ,
U1210A , U1220A , and
U1220B
.
The last
unit ,
U1220B , is
shown separately on
the
block diagram as the Count Gate Control . However , since
the circuit operates essentially in unison , it is discussed in
detail
with
the
other logic
control
circuits
. Loop
Cycle
Counter
eration is also
discussed
in
this part of the
description .
Theory of Operation - FG 5010
Operation of this
circuit
is in
two
modes
,
Frequency Con
trol and
Phase
- Lock
Delay
.
Thus , the
description
discusses
each
separately .
Frequency Control . In this mode , pin 5 of U1310B is
held high to
disable
the Lock
Detector output at
U1210C pin
9 from passing to the CPU through U1430 , and to enable
the start
pulse from
the CPU
through
U1212B
to
pass
through
U1210A
. At the
outset
,
U1212B
pin 4
is high . This
clears
the
Reference
Counter in
preparation for
the mea
surement .
When the
signal falls low ,
the
negataive
edge
pro
vides
the
start of
the
operation
.
Also at the beginning , latches U1122 and U1112 are
loaded by the
CPU with the
number to be
decremented
by
the Loop Cycle Counter . While the CPU start signal is low at
U1212B
pin 3
, this causes
U1222C
pin
10 to be low
,
resetting U1220B , and loading the counters with the num
ber from the
latches
. The
counters
will
not
decrement until
the
load
input
returns
high
.
The negative edge at U1220A sets the flip - flop , since the
J input is always high , and neither the Reference Counter
nor the Loop Cycle Counter outputs are high at the inputs of
U1222A . From pin 13 of U1220A , the CPU is informed that
the Loop Cycle is ready to run , via U1430 pin 5. From
U1220A , the high at the pin 7 input of U1220B arms the flip
flop to set on the next negative edge that arrives from the
Decade
Divider
circuit .
When the flip -
flop sets ,
three
events
occur : Pin 9 of the flip - flop pulls high on the load inputs to
the
counter
,
and the
next
positive edge of the
same signal
from the
Decade
Divider
(
U1222B pin 4 )
begins
the
decrementing operation . Second , the pin 8 output of
U1220B pulls pin
12 of U1222D
low to begin
passing 4 MHz
signal to the
Reference
Counter
. Third , the
same line is con
nected to U1430
pin 15 to tell the
CPU that the
loop counter
is
running .
When the Loop
cycle Counter
reaches zero ,
U1230A pin
6 moves high . This arms U1220B to reset , and resets
U1220A immediately , by way of U1222A . Since U1220A is
now reset ,
U1220B
can
reset on the next
negative
edge
of
the clocking signal from U1222B , which will not decrement
the counters further . The counters are loaded again , and the
circuit will wait for the next trigger from the CPU . The pin 8
output of U1220B is now high , so the 4 MHz clock signal is
blocked
at
U1222D
. The
Reference
Counter
now has
a
number
stored that is
a
function of
the
loop
frequency ,
which is later interrogated by the CPU .
If the
Reference
Counter
overflows
during the
measure
ment , U1322 pin 12 pulls high on pin 9 of U1222C , which
will immediately reset U1220B , bringing the measurement to
a halt . The same line to pin 1 of U1430 tells the CPU of the
overflow , so that appropriate action can be taken .
4-27

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English