Appendix A: Specifications
Trigger
Source, D C coupled Sensitivity
Any channel ±0.2 divisions
External trigger ±20 mV
External/10 trigger
±200 mV
Trigger
level
accuracy,
typical
Line
N/A
Trigger
holdoff
range
250.8 ns to 10 s
Logic an d
Pulse
Trigger
Sensitivity,
typical
1.0 d ivision at BNC, DC Coupled, ≥10 mV/div to ≤ 1V/div
(pattern, state, delay, width, and runt triggering)
Slew Rate
Trigger
Sensitivity,
typical
Same as the Edge Trigger Sensitivity specifications shown
earlier in this a ppendix.
State
Pattern Pattern with pulse width
2ns 2ns
5ns
Logic
Triggering
Minimum
Logic Time,
typical
State
minimum logic time: the time that a logic s tate must
be va
lid be fore and after t he clock edge to be recognized.
Patt
ern minimum logic time: the time that a logic pattern
mus
t be valid to be recognized. Pattern with pulse width
qua
lification, minimum logic time: the time that a logic pattern
mu
st be valid to be recognized.
State
Pattern Pattern with pulse width
4ns
2
2ns
5ns
Logic
Triggering
Minimum
Rearm
Time,
typical
State minimum rearm time: the time between consecutive
clocks. Pattern minimum rearm time: the time that a
logic pattern must be invalid before a new occurrence o f
the pattern will be recognized. Pattern with pulse width
qualification, minimum rearm time: the time that a logic
pattern must be invalid before a new occurrence of the
pattern will be recognized.
156 TDS3000C Series Oscilloscope User Manual