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Texas Instruments Jacinto 7 DRA829 - Configured States

Texas Instruments Jacinto 7 DRA829
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6.1 Configured States
In this PDN, the PMIC devices have the following four configured power states:
Standby
Active
MCU Only
Pwr SoC Error
DDR Retention
In Figure 6-1, the configured PDN power states are shown, along with the transition conditions to move between
the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are
shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the
TPS6594-Q1 data sheet, see Section 8.
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUC99 – JANUARY 2022
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Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
7 DRA829 or
TDA4VM Automotive PDN-0C
31
Copyright © 2022 Texas Instruments Incorporated

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