Appendix A
Table A-4. BSL Version 1.60 on F11x2, F12x2, F43x, F44x, FE42x, FW42x, FG43x, F415, F417
FE42x,
F1122, F1222, F43x,
Device FW42x, FG43x
F1132 F1232 F44x
F41(5,7)
BSL Version 1.60
Cold start 0C00h
BSL vector address
Warm start 0C02h
Chip ID address 0FF0h
Chip ID data 1132h 1232h F449h F427h F439h
BSL version address 0FFAh
BSL version data 0160h
Mass erase time, nominal (ms) 206.4
Read/write access 0000h–00FFh Byte
at
0100h–FFFEh Word
Verification during write (online) For addresses 0200h-FFFEh
Erase check command Yes (error address 0200h)
Erase segment command With erasure verification (error address 0200h)
TX identification command Yes
Change baud rate command Yes
Stack pointer Cold start 0220h
initialization
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.1 P1.0
Receive pin (RX) P2.2 P1.1
RAM/stack used 0200h–021Fh
Working registers R5–R12
System clock, affected controls BCSCTL1, DCOCTL SCFI0, SCFI1, SCFQCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
mov.b #00h, &BCSCTL2 mov.b #00h, &FLLCTL1
Preparation for SW call
mov #00h, SR br &0C00h
br &0C00h
Comment Erase segment Addresses 1000h to 11FFh are verified coherently (3 segments). Also use erase check
command command.
SLAA089D – December 1999 – Revised August 2006 Features of the MSP430 Bootstrap Loader 19
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