Appendix A
Table A-6. BSL Version 2.01 on F21x1, F22xx
Device F21x1 F22xx
BSL Version 2.01
Cold start 0C00h
BSL vector address
Warm start 0C02h
(1)
Chip ID address 0FF0h
Chip ID data F123h F227h
BSL version address 0FFAh
BSL version data 0140h
Mass erase time, nominal (ms) 206.4
Read/write access at 0000h–00FFh Byte
0100h–FFFEh Word
Verification during write (online) For addresses 0200h-FFFEh
Erase check command Yes (error addr 0200h)
Erase segment command With erasure verification (error addr 0200h)
TX identification command Yes
Change baud rate command Yes
Stack pointer Cold start 0220h
initialization
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.1
Receive pin (RX) P2.2
RAM/stack used 0200h–021Fh
Working registers R5–R14
System clock, affected controls BCSCTL1, DCOCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
mov.b #00h, &BCSCTL2
Preparation for SW call
mov #00h, SR
br &0C00h
Comment Erase segment command Addresses 1000h to 11FFh are verified coherently (5 segments).
Also use erase check command.
(1)
The LOCK and LOCKA bits must be cleared by the user application before entering the BSL mov.w #FWKEY+LOCKA, &FCTL3
SLAA089D – December 1999 – Revised August 2006 Features of the MSP430 Bootstrap Loader 21
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