Timer
Note:
Because there is a write buffer in the Cortex-M4 processor, it may take several clock cycles
before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt
source be cleared early in the interrupt handler (as opposed to the very last action) to avoid
returning from the interrupt handler before the interrupt source is actually cleared. Failure to
do so may result in the interrupt handler being immediately reentered (because the interrupt
controller still sees the interrupt source asserted).
Returns:
None.
21.2.1.10 ROM_TimerIntDisable
Disables individual timer interrupt sources.
Prototype:
void
ROM_TimerIntDisable(uint32_t ui32Base,
uint32_t ui32IntFlags)
ROM Location:
ROM_APITABLE is an array of pointers located at 0x0100.0010.
ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11].
ROM_TimerIntDisable is a function pointer located at ROM_TIMERTABLE[20].
Parameters:
ui32Base is the base address of the timer module.
ui32IntFlags is the bit mask of the interrupt sources to be disabled.
Description:
Disables the indicated timer interrupt sources. Only the sources that are enabled can be re-
flected to the processor interrupt; disabled sources have no effect on the processor.
The ui32IntFlags parameter has the same definition as the ui32IntFlags parameter to
ROM_TimerIntEnable().
Returns:
None.
21.2.1.11 ROM_TimerIntEnable
Enables individual timer interrupt sources.
Prototype:
void
ROM_TimerIntEnable(uint32_t ui32Base,
uint32_t ui32IntFlags)
ROM Location:
ROM_APITABLE is an array of pointers located at 0x0100.0010.
ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11].
ROM_TimerIntEnable is a function pointer located at ROM_TIMERTABLE[19].
238 April 8, 2013
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