Texas Instruments Tiva TM4C123GH6PM User Manual

Analog to Digital Converter (ADC)
5.2.1.13 ROM_ADCPhaseDelayGet
Gets the phase delay between a trigger and the start of a sequence.
Prototype:
uint32_t
ROM_ADCPhaseDelayGet(uint32_t ui32Base)
ROM Location:
ROM_APITABLE is an array of pointers located at 0x0100.0010.
ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5].
ROM_ADCPhaseDelayGet is a function pointer located at ROM_ADCTABLE[25].
Parameters:
ui32Base is the base address of the ADC module.
Description:
This function gets the current phase delay between the detection of an ADC trigger event and
the start of the sample sequence.
Returns:
Returns the phase delay, specified as one of ADC_PHASE_0, ADC_PHASE_22_5,
ADC_PHASE_45, ADC_PHASE_67_5, ADC_PHASE_90, ADC_PHASE_112_5,
ADC_PHASE_135, ADC_PHASE_157_5, ADC_PHASE_180, ADC_PHASE_202_5,
ADC_PHASE_225, ADC_PHASE_247_5, ADC_PHASE_270, ADC_PHASE_292_5,
ADC_PHASE_315, or ADC_PHASE_337_5.
5.2.1.14 ROM_ADCPhaseDelaySet
Sets the phase delay between a trigger and the start of a sequence.
Prototype:
void
ROM_ADCPhaseDelaySet(uint32_t ui32Base,
uint32_t ui32Phase)
ROM Location:
ROM_APITABLE is an array of pointers located at 0x0100.0010.
ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5].
ROM_ADCPhaseDelaySet is a function pointer located at ROM_ADCTABLE[24].
Parameters:
ui32Base is the base address of the ADC module.
ui32Phase is the phase delay, specified as one of ADC_PHASE_0, ADC_PHASE_22_5,
ADC_PHASE_45, ADC_PHASE_67_5, ADC_PHASE_90, ADC_PHASE_112_5,
ADC_PHASE_135, ADC_PHASE_157_5, ADC_PHASE_180, ADC_PHASE_202_5,
ADC_PHASE_225, ADC_PHASE_247_5, ADC_PHASE_270, ADC_PHASE_292_5,
ADC_PHASE_315, or ADC_PHASE_337_5.
Description:
This function sets the phase delay between the detection of an ADC trigger event and the start
of the sample sequence. By selecting a different phase delay for a pair of ADC modules (such
44 April 8, 2013

Texas Instruments Tiva TM4C123GH6PM Specifications

General

Core	ARM Cortex-M4F
Clock Speed	80 MHz
Flash Memory	256 KB
SRAM	32 KB
GPIO Pins	43
UART	8
I2C	2
SPI/SSI	4
USB	USB 2.0
Timers	6
Communication Interfaces	UART, I2C, SPI, USB
Operating Temperature	-40°C to 85°C
Package	LQFP64

Summary

Boot Loader

Introduction

Explains the ROM-based boot loader and its interfaces for flash updates.

Serial Interfaces

Details the UART, SSI, and I2C interfaces used by the boot loader.

USB Interface

Describes the USB boot loader functionality using the DFU protocol.

Controller Area Network (CAN)

Flash

GPIO

Hibernation Module

Inter-Integrated Circuit (I2C)

Interrupt Controller (NVIC)

Memory Protection Unit (MPU)

Pulse Width Modulator (PWM)

Synchronous Serial Interface (SSI)

System Control

Timer

UART

uDMA Controller

USB Controller

Using USB with the uDMA Controller

Watchdog Timer

Introduction

Functions

Lists and describes API functions for watchdog timer configuration, interrupts, and lock mechanism.