Texas Instruments TMS320C6455

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List of Tables
1 DDR2 Memory Controller Signal Descriptions......................................................................... 12
2 DDR2 SDRAM Commands .............................................................................................. 13
3 Truth Table for DDR2 SDRAM Commands............................................................................ 13
4 Addressable Memory Ranges ........................................................................................... 20
5 Bank Configuration Register Fields for Address Mapping ........................................................... 21
6 DDR2 Memory Controller FIFO Description ........................................................................... 24
7 Refresh Urgency Levels .................................................................................................. 27
8 Device and DDR2 Memory Controller Reset Relationship........................................................... 28
9 DDR2 SDRAM Mode Register Configuration.......................................................................... 29
10 DDR2 SDRAM Extended Mode Register 1 Configuration ........................................................... 29
11 SDCFG Configuration..................................................................................................... 35
12 DDR2 Memory Refresh Specification .................................................................................. 36
13 SDRFC Configuration..................................................................................................... 36
14 SDTIM1 Configuration .................................................................................................... 36
15 SDTIM2 Configuration .................................................................................................... 37
16 DMCCTL Configuration................................................................................................... 37
17 DDR2 Memory Controller Registers .................................................................................... 38
18 Module ID and Revision Register (MIDR) Field Descriptions ....................................................... 39
19 DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions ....................................... 40
20 SDRAM Configuration Register (SDCFG) Field Descriptions ....................................................... 41
21 SDRAM Refresh Control Register (SDRFC) Field Descriptions .................................................... 43
22 SDRAM Timing 1 Register (SDTIM1) Field Descriptions ............................................................ 44
23 SDRAM Timing 2 Register (SDTIM2) Field Descriptions ............................................................ 46
24 Burst Priority Register (BPRIO) Field Descriptions ................................................................... 47
25 DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions ........................................ 48
5
SPRU970G– December 2005– Revised June 2011 List of Tables
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