Texas Instruments TMS320C6455

Texas Instruments TMS320C6455

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6

List of Tables SPRU970G– December 2005– Revised June 2011

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Copyright © 2005–2011, Texas Instruments Incorporated

Table of Contents

Default Chapter3
- Table of Contents3
Preface7
Introduction9
Peripheral Architecture11
- Clock Control11
- Memory Map11
- Signal Descriptions11
- DDR2 Memory Controller Signals12
- DDR2 Memory Controller Signal Descriptions12
  - Protocol Description(S)13
- DDR2 SDRAM Commands13
- Truth Table for DDR2 SDRAM Commands13
- DDR2 MRS and EMRS Command14
- Refresh Command15
- ACTV Command16
- DCAB Command17
- DEAC Command18
- DDR2 READ Command19
  - Memory Width, Byte Alignment, and Endianness20
- DDR2 WRT Command20
- Addressable Memory Ranges20
  - Address Mapping21
- Byte Alignment21
- Bank Configuration Register Fields for Address Mapping21
- Logical Address-To-DDR2 SDRAM Address Map for 32-Bit SDRAM22
- Logical Address-To-DDR2 SDRAM Address Map for 16-Bit SDRAM22
- Logical Address-To-DDR2 SDRAM Address Map23
  - DDR2 Memory Controller Interface24
- DDR2 SDRAM Column, Row, and Bank Access24
- DDR2 Memory Controller FIFO Description24
- DDR2 Memory Controller FIFO Block Diagram25
  - Refresh Scheduling27
- Refresh Urgency Levels27
  - Self-Refresh Mode28
  - 2.10 Reset Considerations28
  - 2.11 DDR2 SDRAM Memory Initialization28
- Device and DDR2 Memory Controller Reset Relationship28
- DDR2 SDRAM Mode Register Configuration29
- DDR2 SDRAM Extended Mode Register 1 Configuration29
  - 2.12 Interrupt Support30
  - 2.13 EDMA Event Support30
  - 2.14 Emulation Considerations30
Using the DDR2 Memory Controller31
DDR2 Memory Controller Registers38
Revision History49
- Important Notice50

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