Texas Instruments TMS320F2837 D Series

www.ti.com Usage Notes and Known Design Exceptions to Functional Specifications
33
SPRZ412K–December 2013–Revised February 2020
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TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0
Advisory Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity
Revision(s) Affected 0, A, B, C
Details The device has an intentional current path from V
DD3VFL
(flash supply) to V
DD
. Since the
HALT, STANDBY, IDLE, or other low-activity device conditions can have low current
demand on V
DD
, this V
DD3VFL
current can cause V
DD
to rise above the recommended
operating voltage.
There will be zero current load to the external system V
DD
regulator while in this
condition. This is not an issue for most regulators; however, some system voltage
regulators require a minimum load for proper operation.
Workaround(s) Workaround 1: Power down the flash before entering HALT, STANDBY, IDLE, or other
low-activity device conditions. This will disable the internal current path. This workaround
must be executed from RAM.
// CPU-1
EALLOW;
// seize the pump semaphore
while (IpcRegs.PUMPREQUEST.bit.SEM != 0x2)
{
IpcRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x2;
}
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0;
asm(" RPT #8 || NOP");
// power down pump
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0;
asm(" RPT #8 || NOP");
// release pump semaphore
IpcRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x0;
EDIS;
// enter low power mode
asm(" IDLE");
// CPU-2
EALLOW;
// seize the pump semaphore
while (IpcRegs.PUMPREQUEST.bit.SEM != 0x1)
{
IpcRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x1;
}
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0;
asm(" RPT #8 || NOP");
// power down pump
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0;
asm(" RPT #8 || NOP");
// release pump semaphore
IpcRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x0;
EDIS;
// enter low power mode
asm(" IDLE");
Workaround 2: Keep SYSCLK at a minimum of 100 MHz during STANDBY or IDLE.
This activity will be sufficient to consume the internal current.
Workaround 3: An external 82-Ω resistor can be added to the board between V
DD
and
V
SS
.