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Usage Notes and Known Design Exceptions to Functional Specifications

SPRZ412K–December 2013–Revised February 2020

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TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0

4.2 Known Design Exceptions to Functional Specifications

Table 3 shows which silicon revision(s) are affected by each advisory.

Table 3. List of Advisories

TITLE

SILICON REVISION(S) AFFECTED

0 A B C

Analog Bandgap References Yes Yes Yes Yes

Analog Trim of Some TMX Devices Yes Yes Yes

ADC: ADC Post-Processing Block Limit Compare Yes Yes Yes Yes

ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes Yes Yes

ADC: ADC Offset Trim in Different Modes Yes Yes Yes Yes

ADC: DMA Read of Stale Result Yes Yes Yes Yes

ADC: Random Conversion Errors Yes Yes Yes

ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule Yes Yes Yes

ADC: 12-Bit Switch Resistance Yes Yes Yes

ADC: 12-Bit Input Capacitance When Switching Channel Groups Yes Yes Yes

ADC: Functionality of V

REFLO

Pins Yes Yes

ADC: Sensitivity to ESD Events Yes Yes

ADC: ADC Input Multiplexer Connection at Beginning of Acquisition Window Yes Yes

ADC: ADC Sparkle Codes Yes Yes

ADC: ADC Linearity Performance Yes

XRS may Toggle During Power Up Yes Yes Yes

USB: USB DMA Event Triggers are not Supported Yes Yes Yes Yes

VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ Yes Yes Yes

Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR Yes Yes Yes Yes

Flash: Minimum Programming Word Size Yes Yes Yes Yes

Flash: Reset of CPU2 While it has Pump Ownership Can Cause Erroneous Flash

Reads From CPU1

Yes Yes

ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled Yes Yes Yes

eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes Yes Yes Yes

eQEP: eQEP Inputs in GPIO Asynchronous Mode Yes Yes Yes Yes

PLL: May Not Lock On the First Lock Attempt Yes Yes Yes Yes

PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective Yes Yes Yes Yes

SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and

OSR = 256

Yes Yes Yes Yes

SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and

Enabled for the First Time

Yes Yes Yes Yes

SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using

PWM FILRES Signal

Yes Yes Yes Yes

SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-

Value Conditions

Yes Yes Yes Yes

SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or

COSR Settings Will Trigger Spurious Comparator Events

Yes Yes Yes Yes

SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR)

Will Trigger Spurious Data Acknowledge Events

Yes Yes Yes Yes

FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes Yes Yes

FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions Yes Yes Yes Yes

Memory: Prefetching Beyond Valid Memory Yes Yes Yes Yes

INTOSC: V

DDOSC

Powered Without V

Can Cause INTOSC Frequency Drift Yes Yes Yes Yes

Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity Yes Yes Yes Yes

I2C: SDA and SCL Open-Drain Output Buffer Issue Yes Yes Yes Yes

Brand	Texas Instruments
Model	TMS320F2837 D Series
Category	Microcontrollers
Language	English

Texas Instruments TMS320F2837 D Series Errata Sheet

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