RM46L852
www.ti.com
SPNS185 –SEPTEMBER 2012
RM46L852 16/32-Bit RISC Flash Microcontroller
Check for Samples: RM46L852
1 RM46L852 16/32-Bit RISC Flash Microcontroller
1.1 Features
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• High-Performance Microcontroller for Safety • Two High-End Timer Modules (N2HET)
Critical Applications
– N2HET1: 32 programmable channels
– Dual CPUs running in lockstep
– N2HET2: 18 programmable channels
– ECC on flash and RAM interfaces
– 160 Word Instruction RAM with parity
– Built-In Self Test for CPU and on-chip RAMs protection each
– Error Signaling Module with Error Pin – Each includes Hardware Angle Generator
– Voltage and Clock Monitoring – Dedicated Transfer Units (HTU) on N2HETs
• ARM® Cortex™ – R4F 32-bit RISC CPU • Two 10/12-bit Multi-Buffered ADC Modules
– 1.66DMIPS/MHz with 8-stage pipeline – ADC1: 24 channels
– FPU with Single/Double Precision – ADC2: 16 channels
– 12-Region Memory Protection Unit – 16 shared channels
– Open Architecture with 3rd Party Support – 64 result buffers with parity protection each
• Operating Conditions • Multiple Communication Interfaces
– Up to 220MHz System Clock – 10/100 Mbps Ethernet MAC (EMAC)
– Core Supply Voltage (VCC): 1.14V - 1.32V • IEEE 802.3 compliant (3.3V-I/O only)
– I/O Supply Voltage (VCCIO): 3.0V - 3.6V • Supports MII, RMII and MDIO
• Integrated Memory – USB (revision 2.0 full-speed)
– 1.25MB Program Flash with ECC • 2-port USB Specification, revision 2.0-
compatible host controller, based on the
– 192KB RAM with ECC
OHCI Specification for USB, release 1.0
– 64KB Flash for emulated EEPROM with ECC
• USB device compatible with the USB
• 16- bit External Memory Interface (EMIF)
Specification, revision 2.0 and USB
• Common Platform Architecture
Specification, revision 1.1
– Consistent memory map across family
– Three CAN Controllers (DCAN)
– Real-Time Interrupt Timer (RTI) OS Timer
• 64 mailboxes with parity protection each
– 128-channel Vectored Interrupt Module (VIM)
• Compliant to CAN protocol version
– 2-channel Cyclic Redundancy Checker (CRC)
2.0A/B
• Direct Memory Access (DMA) Controller
– Inter-Integrated Circuit (I
2
C)
– 16 Channels and 32 Control Packets
– Three Multi-buffered Serial Peripheral
– Parity protection for control packet RAM
Interfaces (MibSPI)
– DMA Accesses Protected by Dedicated MPU
• 128 Words with Parity Protection each
• Frequency-Modulated Phase-Locked-Loop
• 8 Transfer groups
(FMPLL) with Built-In Slip Detector
– Up to two Standard Serial Peripheral
• Separate Non-Modulating PLL
Interfaces (SPI)
• IEEE 1149.1 JTAG, Boundary Scan and ARM
– Two UART (SCI) interfaces, one with Local
CoreSight Components
Interconnect Network Interface (LIN 2.1)
• Advanced JTAG Security Module (AJSM)
Support
• Trace and Calibration Capabilities
• Up to 101 general purpose I/O (GIO) capable
pins
– Parameter Overlay Module (POM)
– 16 dedicated GIO pins with interrupt
• Enhanced Timing Peripherals for Motor Control
generation capability
– 7 Enhanced Pulse Width Modulators (ePWM)
• Packages
– 6 Enhanced Capture (eCAP)
– 144-pin Quad Flatpack (PGE) [Green]
– 2 Enhanced Quadrature Encoder Pulse
– 337-Ball Grid Array (ZWT) [Green]
(eQEP)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or design phase of
Copyright © 2012, Texas Instruments Incorporated
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
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