RM46L852
SPNS185 –SEPTEMBER 2012
www.ti.com
2.3 Terminal Functions
Section 2.3.1 and Section 2.3.2 identify the external signal names, the associated pin/ball numbers along
with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether
the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GIO, and a
functional pin/ball description. The first signal name listed is the primary function for that terminal. The
signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) User
Guide for information on how to select between different multiplexed functions.
NOTE
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately
after nPORRST goes High.
All output-only signals are configured as inputs while nPORRST is low, and are configured
as outputs immediately after nPORRST goes High.
While nPORRST is low, the input buffers are disabled, and the output buffers are tri-stated.
2.3.1 PGE Package
2.3.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)
Table 2-1. PGE Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal Signal Default Pull Type Description
Type Pull State
Signal Name 144
PGE
ADREFHI
(1)
66 Power - - ADC high reference
supply
ADREFLO
(1)
67 Power ADC low reference supply
VCCAD
(1)
69 Power Operating supply for ADC
VSSAD
(1)
68 Ground
AD1EVT/MII_RX_ER/RMII_RX_ER 86 Input Pull Down Programmable, ADC1 event trigger input,
20uA or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ 55 I/O Pull Up Programmable, ADC2 event trigger input,
EQEP1I/N2HET2_PIN_nDIS 20uA or GIO
AD1IN[0] 60 Input - - ADC1 analog input
AD1IN[01] 71
AD1IN[02] 73
AD1IN[03] 74
AD1IN[04] 76
AD1IN[05] 78
AD1IN[06] 80
AD1IN[07] 61
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
10 Device Package and Terminal Functions Copyright © 2012, Texas Instruments Incorporated
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