Main Cross Bar: Arbitration and Prioritization Control
CRC
Switched Central Resource
Peripheral Central Resource Bridge
Dual Cortex-R4F
CPUs in Lockstep
DCAN1
DCAN2
DCAN3
LIN
SCI
SPI4
64 KB Flash
for EEPROM
Emulation
with ECC
MibSPI1
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MibSPI3
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MibSPI5
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
LIN_RX
LIN_TX
SCI_RX
SCI_TX
IOMM
PMM
VIM
RTI
DCC1
DCC2
32K
32K
32K
192kB RAM
with ECC
MibADC1 MibADC2
I2C
N2HET1
GIO
I2C_SCL
I2C_SDA
GIOB[7:0]
GIOA[7:0]
AD1EVT
AD1IN[7:0]
AD2EVT
# 2
# 3
# 5
# 1
# 2
# 1
always on
Core/RAM
RAM
Core
Color Legend for
Power Domains
SYS
nPORRST
nRST
ECLK
ESM
nERROR
1.25MB
Flash
with
ECC
32K
32K
32K
Switched
Central Resource
Switched Central Resource
N2HET2[18,16]
N2HET2[15:0]
N2HET1[31:0]
N2HET1_PIN_nDIS
N2HET2_PIN_nDIS
VSSAD
VCCAD
ADREFHI
ADREFLO
N2HET2
AD1IN[15:8] \
AD2IN[15:8]
AD1IN[23:16] \
AD2IN[7:0]
EMAC Slaves
MDIO
MII
MDCLK
MDIO
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
MII_CRS
MII_RXDV
MII_COL
EMIF
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[12:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_nRW
EMIF_nWAIT
eQEP
1,2
eQEPxA
eQEPxB
eQEPxS
eQEPxI
eCAP
1..6
eCAP[6:1]
ePWM
1..7
nTZ[3:1]
SYNCO
SYNCI
ePWMxA
ePWMxB
Device
Host
USB1.OverCurrent
USB1.RCV
USB1.VM
USB1.VP
USB1.PortPower
USB1.SPEED
USB1.SUSPEND
USB1.TXDAT
USB1.TXEN
USB1.TXSE0
USB2.OverCurrent
USB2.RCV
USB2.VM
USB2.VP
USB2.PortPower
USB2.SPEED
USB2.SUSPEND
USB2.TXDAT
USB2.TXEN
USB2.TXSE0
USB_FUNC.GZO
USB_FUNC.PUENO
USB_FUNC.PUENON
USB_FUNC.RXDI
USB_FUNC.RXDMI
USB_FUNC.RXDPI
USB_FUNC.SE0O
USB_FUNC.SUSPENDO
USB_FUNC.TXDO
USB_FUNC.VBUSI
USB Slaves
HTU1 HTU2
Switched
Central Resource
DMA POM
Switched
Central Resource
Switched
Central Resource
EMAC OHCI
RM46L852
www.ti.com
SPNS185 –SEPTEMBER 2012
1.4 Functional Block Diagram
NOTE
The block diagram reflects the 337BGA package. Some pins are multiplexed or not available
in the 144QFP. Please see the Terminal functions table for details.
Figure 1-1. Functional Block Diagram
Copyright © 2012, Texas Instruments Incorporated RM46L852 16/32-Bit RISC Flash Microcontroller 5
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