EMIF_nCS[3:2]
EMIF_BA[1:0]
13
12
EMIF_ADDR[12:0]
EMIF_nOE
EMIF_DATA[15:0]
EMIF_nWE
10
5
9
7
4
8
6
3
1
EMIF_nDQM[1:0]
30
29
RM46L852
SPNS185 –SEPTEMBER 2012
www.ti.com
4.14 External Memory Interface (EMIF)
4.14.1 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external
asynchronous memories or SDRAM devices. The EMIF features includes support for:
• 3 addressable chip select for asynchronous memories of up to 32kB each
• 1 addressable chip select space for SDRAMs up to 128MB
• 8 or 16-bit data bus width
• Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
• Select strobe mode
• Extended Wait mode
• Data bus parking
4.14.2 Electrical and Timing Specifications
4.14.2.1 Read Timing (Asynchronous RAM)
Figure 4-12. Asynchronous Memory Read Timing
88 System Information and Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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