EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_nWE
EMIF_DATA[15:0]
EMIF_nOE
15
1
16
18
20
22
24
17
19
21
23
26
27
EMIF_nDQM[1:0]
EMIF_nCS[3:2]
11
Asserted Deasserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_DATA[15:0]
EMIF_nOE
EMIF_WAIT
SETUP
Extended Due to EMIF_WAIT
STROBE HOLD
14
STROBE
RM46L852
www.ti.com
SPNS185 –SEPTEMBER 2012
Figure 4-13. EMIFnWAIT Read Timing Requirements
4.14.2.2 Write Timing (Asynchronous RAM)
Figure 4-14. Asynchronous Memory Write Timing
Copyright © 2012, Texas Instruments Incorporated System Information and Electrical Specifications 89
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