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Usage Notes and Known Design Exceptions to Functional Specifications
41
SPRZ412K–December 2013–Revised February 2020
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TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0
Advisory During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the
FIFO Buffer
Revision(s) Affected 0, A, B, C
Details In DCAN FIFO mode, received messages with the same arbitration and mask IDs are
supposed to be placed in the FIFO in the order in which they are received. The CPU
then retrieves the received messages from the FIFO via the IF1/IF2 interface registers.
Some messages may be placed in the FIFO out of the order in which they were
received. If the order of the messages is critical to the application for processing, then
this behavior will prevent the proper use of the DCAN FIFO mode.
Workaround(s) None
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