Toshiba e-studio 160 - Page 96

e-STUDIO160/200/250 DISPLAY UNIT 5 - 16 December 2002 TOSHIBA TEC
(4) LCD Controller Block Diagram
(5) Data Transmission Method
System
Resister
Address
Main board
SRAM
Data
Address
FLM
SD
LP
SCP
Clock
Data
SRAM
control
Timing
generator
Bit check
control
Attribute
control
Line
memory
control
Line
memory
CPI (LP)
64 1
FLM
240
48,240 1,1 1,2 1,240 2,1
1 2 3 240 1 2
CP2 (SCP)
CPI (LP)
D
64, (1~240) 1, (1~240) 2, (1~240) 1, (1~240)
D
63 64 641 2 1