TYAN S8030 - Page 88

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3.5.1 CPU Common Options
CCD/Core/Thread Enablement
CCD/Core/Thread Enablement.
Prefetcher Settings
Prefetcher Settings.
Platform First Error Handling
Enable/disable PFEH, cloak individual banks, and mask deferred error interrupts
from each bank.
Enabled / Disabled / Auto
Core Performance Boost
Disable CPB.
Disabled / Auto
Global C-state Control
Controls IO based C-state generation and DF C-states.
Disabled / Enabled / Auto