Chapter 3 Deployment IM 253DP Manual VIPA System 200V
3-46 HB97E - IM - RE_253-xDPxx - Rev. 12/44
The CPU should have a short cycle time to ensure that the data from slave
no. 5 (on the right) is always up to date. This type of structure is only
suitable when the data from slaves on the slow trunk (on the left) is not
critical. You should therefore not connect modules that are able to issue
alarms.
IM 253
1
Input/output periphery
IM 253
2
Input/output periphery
IM 253
4
Input/output periphery
IM 253
5
Input/output periphery
CPU IM 208
1,2,
3,4
IM 208
5
IM 253
3
Input/output periphery
CPU with
short cycle time
subject to fast updates.
For short CPU cycle times the data
of IM-interface no. 5 is always up to date.
slow due to the large number of
interfaces, i.e. transferred data is
not always up to date
Example for a
PROFIBUS
network
One CPU and
multiple master
connections
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