Xilinx LogiCORE 1000BASE-X - Page 14

www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
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Table 9-21: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 9-22: SGMII Auto-Negotiation Advertisement (Register 4) . . . . . . . . . . . . . . . . . . 139
Table 9-23: SGMII Auto-Negotiation Link Partner Ability Base (Register 5) . . . . . . . . 140
Table 9-24: SGMII Auto-Negotiation Expansion (Register 6) . . . . . . . . . . . . . . . . . . . . . . 141
Table 9-25: SGMII Auto-Negotiation Next Page Transmit (Register 7). . . . . . . . . . . . . . 141
Table 9-26: SGMII Auto-Negotiation Next Page Receive (Register 8) . . . . . . . . . . . . . . . 142
Table 9-27: SGMII Extended Status Register (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 9-28: SGMII Auto-Negotiation Interrupt Control (Register 16). . . . . . . . . . . . . . . 144
Table 9-29: MDIO Registers for 1000BASE-X with Auto-Negotiation. . . . . . . . . . . . . . . 145
Table 9-30: SGMII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 9-31: SGMII Status (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 9-32: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 9-33: SGMII Auto-Negotiation Advertisement (Register 4) . . . . . . . . . . . . . . . . . . 149
Table 9-34: SGMII Extended Status Register (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 9-35: Vendor-specific Register: Standard Selection Register (Register 17) . . . . . 151
Table 9-36: Optional Configuration and Status Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Chapter 12: Constraining the Core
Table 12-1: Input TBI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 12-2: Input GMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Appendix D: 1000BASE-X State Machines
Table D-1: Defined Ordered Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Appendix E: Rx Elastic Buffer Specifications
Table E-1: Maximum Frame Sizes: RocketIO Transceiver Rx Elastic Buffers
(100ppm Clock Tolerance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table E-2: Maximum Frame Sizes: Fabric Rx Elastic Buffers
(100ppm Clock Tolerance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table E-3: Maximum Frame Size: (Sustained Frame Reception)
Capabilities of the Rx Elastic Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226