Xilinx LogiCORE 1000BASE-X - Page 65

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 65
UG155 March 24, 2008
Implementing External GMII
R
Virtex-5 Devices
Figure 5-17 illustrates how to create an external GMII transmitter in a Virtex-5 family
device. The signal names and logic shown on the figure exactly match those delivered with
the example design.
The IODELAY elements can be adjusted to fine-tune the setup and hold times at the GMII
IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the
UCF; these can be edited if desired. See “Constraints When Implementing an External
GMII” in Chapter 12 for more information.
Figure 5-17: External GMII Transmitter Logic for Virtex-5 Devices
gmii_tx_clk
IBUFG
IOB LOGIC
IPAD
gmii_txd[0]
IBUF
D
Q
gmii_tx_en
gmii_tx_er
gmii_txd[0]
gmii_tx_en
gmii_tx_er
BUFG
Ethernet 1000BASE-X
PCS/PMA
or SGMII LogiCORE
IPAD
IPAD
IPAD
IBUF
IBUF
D
Q
D
Q
gmii_tx_clk_bufg
gmii_txd_int[0]
gmii_tx_en_int
gmii_tx_er_int
Transmitter
Elastic
Buffer
userclk2 (if RocketIO is used)
gtx_clk (if TBI is used)
IODELAY
IODELAY
IODELAY
IODELAY