Xilinx SP701 - Appendix B: Xilinx Design Constraints; Overview

Appendix B
Xilinx Design Constraints
Overview
The Xilinx design constraints (XDC) le template for the SP701 board provides for designs
targeng the SP701 evaluaon board. Net names in the constraints le correlate with net names
on the latest SP701 evaluaon board schemac. Idenfy the appropriate pins and replace the net
names with net names in the user RTL. See the Vivado Design Suite User Guide: Using Constraints
(UG903) for more informaon.
The FMC LPC connector J21 is connected to FPGA banks powered by the variable voltage V
ADJ
(1.8V nominal). Because dierent FMC cards implement dierent circuitry, the FMC bank I/O
standards must be uniquely dened by each customer.
IMPORTANT!
See the SP701 board website documentaon tab (Board Files check box) for the XDC le.
UG1319 (v1.0) July 12, 2019 www.xilinx.com
SP701 Board User Guide 45
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