Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT - Page 19

VC7203 IBERT Getting Started Guide www.xilinx.com 19
UG847 (v4.0) November 6, 2013
Running the GTX IBERT Demonstration
3. The Vivado tool now shows the SuperClock-2 VIO core and the IBERT core. To
configure the SuperClock-2 module, select Tools > Run Tcl Script (Figure 1-15). In the
following Run Script window, navigate to the setup_scm2_156_25.tcl script in
the extracted files and click OK.
4. To view the SuperClock 2 settings in the VIO core, select the following signals:
u_scm2/u_vio_sclk2_control/si570_start
u_scm2/u_vio_sclk2_control/si570_addr[6:0]
u_scm2/u_vio_sclk2_control/si5368_start
u_scm2/u_vio_sclk2_control/si5368_addr[6:0]
X-Ref Target - Figure 1-15
Figure 1-15: Run Tcl Script...
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