Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT - Page 38

38 www.xilinx.com VC7203 IBERT Getting Started Guide
UG847 (v4.0) November 6, 2013
Chapter 1: VC7203 IBERT Getting Started Guide
16. When the Synthesized Design opens, select dbg_hub in the Netlist window, then
select the Debug Core Options tab in the Cell Properties window and change
C_USER_SCAN_CHAIN* to 2 (Figure 1-32). Click File > Save Constraints.
X-Ref Target - Figure 1-32
Figure 1-32: Debug Core Options for dbg_hub
8*BFBB
Send Feedback