Xilinx Virtex-7 FPGA VC7203 - Page 13

VC7203 IBERT Getting Started Guide www.xilinx.com 13
UG847 (v3.0) July 10, 2013
Running the GTX IBERT Demonstration
ADR2=ON, ADR1=OFF, and ADR0=ON. The MODE bit (switch position 4) is not
used and can be set either ON or OFF.
5. Place the main power switch SW1 to the ON position.
There is one IBERT demonstration design for each GTX Quad on the VC7203 board, for a
total of seven IBERT designs. An additional design is provided to demonstrate the
USB/UART interface (details of this demonstration are described in the README file on the
SD card). All eight designs are organized and stored on the SD card as shown in Table 1-1.
X-Ref Target - Figure 1-9
Figure 1-9: Configuration Address DIP Switch (SW8)
Table 1-1: SD Card Contents and Configuration Addresses
Demonstration
Design
ADR2 ADR1 ADR0
GTX Quad 113ONONON
GTX Quad 114 ON ON OFF
GTX Quad 115 ON OFF ON
GTX Quad 116 ON OFF OFF
GTX Quad 117 OFF ON ON
GTX Quad 118 OFF ON OFF
GTX Quad 119 OFF OFF ON
USB/UART OFF OFF OFF
UG847_c1_09_110112
ADR0
ADR1
ADR2
SYSACE-2 CFG
2 3
4
SW8
1
MODE
ON